Dean A. Mulla

Data Cache design considerations for the Itanium/sub /spl reg// 2 Processor

The second member in the Itanium Processor Family, the Itanium 2 processor, was designed to meet the challenge for high performance in todays technical and commercial server applications. The Itanium 2 processors data cache microarchitecture provides abundant memory resources, low memory latencies and cache organizations tuned to for a variety of applications. The data cache design provides four memory ports to support the many performance optimizations available in the EPIC (Explicitly Parallel Instruction Computing) design concepts, such as predication, speculation and explicit prefetching. The three-level cache hierarchy provides a 16KB 1-cycle first level cache to support the moderate bandwidths needed by integer applications. The second level cache is 256KB with a relatively low latency and FP balanced bandwidth to support technical applications. The onchip third level cache is 3MB and is designed to provide the low latency and the large size needed by commercial and technical applications.