Eric Delano

Performance features of the PA7100 microprocessor

The PA7100 CPU, the first precision-architecture, reduced-instruction-set-computer (PA-RISC) architecture implementation to combine an integer core and floating-point coprocessor into a single-chip format, is described. It incorporates superscalar execution and supports clock rates of up to 100 MHz in standard 0.8- mu m CMOS. Features such as a flexible primary cache organization and multiprocessing capability allow the device to be scaled to a variety of system applications, price ranges, and performance levels. The microprocessor instruction execution pipeline, cache design, translation look-aside buffer (TLB) for virtual address translation, floating-point unit, and system interface bus are discussed. The design, test, and verification methods used in the development of the PA7100 are reviewed.<<ETX>>

PA7200: a PA-RISC processor with integrated high performance MP bus interface

A new processor implementing Hewlett-Packards PA-RISC 1.1 (Precision Architecture) has been designed. This latest design incorporates many improvements over the HP PA7100 CPU, including increased frequency, instruction and data cache prefetching, enhanced superscalar execution, and enhanced multiprocessor support. The PA7200 connects directly to a new split transaction, 120 MHz, 64-bit bus capable of supporting multiple processors and multiple outstanding memory reads per processor. A novel fully associative on-chip data cache, which is accessed in parallel with an external data cache, is used to reduce the miss rate and facilitate hardware and software directed prefetching to reduce average memory access time.<<ETX>>

A high speed superscalar PA-RISC processor

A novel processor implementing Hewlett-Packards PA-RISC 1.1 (precision architecture-reduced instruction set computer) has been designed. A single chip implemented in a 0.8- mu m three-level metal CMOS technology includes the integer processor and a floating point coprocessor. The design operates at 100 MHz and is the first superscalar PA-RISC design. The processor cache is a large configurable memory implemented with industry standard SRAMs (static RAMs). High performance is achieved by high-frequency operation and a variety of techniques used to reduce the average number of cycles per instruction.<<ETX>>

Data Cache design considerations for the Itanium/sub /spl reg// 2 Processor

The second member in the Itanium Processor Family, the Itanium 2 processor, was designed to meet the challenge for high performance in todays technical and commercial server applications. The Itanium 2 processors data cache microarchitecture provides abundant memory resources, low memory latencies and cache organizations tuned to for a variety of applications. The data cache design provides four memory ports to support the many performance optimizations available in the EPIC (Explicitly Parallel Instruction Computing) design concepts, such as predication, speculation and explicit prefetching. The three-level cache hierarchy provides a 16KB 1-cycle first level cache to support the moderate bandwidths needed by integer applications. The second level cache is 256KB with a relatively low latency and FP balanced bandwidth to support technical applications. The onchip third level cache is 3MB and is designed to provide the low latency and the large size needed by commercial and technical applications.

A CMOS RISC CPU with on-chip parallel cache

This CMOS CPU in a 0.55 /spl mu/m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz). Chip parameters are given.<<ETX>>

A CMOS RISC CPU designed for sustained high performance on large applications

A 90-MHz CMOS CPU has been designed for sustained performance in workstation and commercial/technical multiuser applications. The CPU is part of a multichip system that achieves a 60-MHz operating frequency with 15-ns asynchronous SRAMs. Key performance features include a 3.5-ns 32-b adder, low skew on-chip clock buffers, and cycling large off-chip caches at the operating frequency. The chip has been fabricated using a 1.0- mu m CMOS process that utilizes three-level metal and 480000 transistors on a 14*14-mm die. >

A 90 MHz CMOS RISC CPU designed for sustained performance

A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both commercial and technical multiuser applications. Key performance features include a 3-ns, 32-b adder; low-skew on-chip clock buffers; and cycling off-chip caches at the operating frequency, using industry-standard synchronous static random-access memories (SRAMs). The speeds obtained are comparable to those of many emitter-coupled logic (ECL) implementations. The CPU chip includes the following hardware: integer fetch and execute unit, on-chip split I/D TLBs (translation lookaside buffers) with two-way 64 entries each, control for second-level off-chip TLBs, control for off-chip two-way split I/D writeback caches with single-bit error correction for data, full multiprocessing support hardware, inference for performance analysis and tuning, and a tightly coupled coprocessor interface.<<ETX>>

A 100 MHz superscalar PA-RISC CPU/coprocessor chip

A RISC CPU chip has been designed for 100-MHz operation. The chip combines a 32-b integer core and a full 64-b floating point coprocessor on a 1.43-cm*1.43-cm die. The chip is fabricated in a 0.8- mu m CMOS process with three layers of aluminum interconnect. It contains in excess of 850000 transistors. Many of the CPU circuits were adapted from an earlier CPU designed for 66 MHz in a 1- mu m-gate process. Careful characterization of that circuit combined with design shrinkage to 0.8 mu m yielded the desired performance. Other circuits were directly designed for 100-MHz operating frequency in the scaled process.<<ETX>>