Debatosh Debnath

A heuristic algorithm to design AND-OR-EXOR three-level networks

An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products expressions (EX-SOP). In this paper, we show an algorithm to simplify EX-SOPs for multiple-output functions. Our objective is to minimize the number of distinct products in the sum-of-products expressions of EX-SOPs. The algorithm uses a divide-and-conquer strategy. It recursively applies the Shannon decomposition on a function with more than five variables. The algorithm obtains EX-SOPs for the five-variable functions by using an exact minimization program, then combines those EX-SOPs to generate EX-SOPs for the functions with more variables. We present experimental results for a set of benchmark functions, and show that EX-SOPs require many fewer products and literals than sum-of-products expressions. This is evidence that AND-OR-EXOR is a powerful architecture to realize many practical logic functions.

Efficient computation of canonical form for Boolean matching in large libraries

This paper presents an efficient technique for solving a Boolean matching problem in cell-library binding, where the number of cells in the library is large. As a basis of the Boolean matching, we use the notion NP-representative (NPR); two functions have the same NPR if one can be obtained from the other by a permutation and/or complementation(s) of the variables. By using a table look-up and a tree-based breadth-first search strategy, our method quickly computes NPR for a given function. Boolean matching of the given function against the whole library is determined by checking the presence of its NPR in a hash table, which stores NPRs for all the library functions and their complements. The effectiveness of our method is demonstrated through experimental results, which shows that it is more than two orders of magnitude faster than the Hinsberger-Kollas algorithm---the fastest Boolean matching algorithm for large libraries.

Multiple-valued minimization to optimize PLAs with output EXOR gates

This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We present techniques to minimize EX-SOPs, which is an extension of Dubrova-Miller-Muzios AOXMIN algorithm. We conjecture that, when n is sufficiently large, an EX-SOP for n-bit adder requires at most 2/sup n/ products while an ordinary sum-of-products expression (SOP) requires 6/spl middot/2/sup n/-4n-5 products. Experimental results for two- and four-valued benchmark functions show that the proposed method produces better EX-SOPs than existing methods.

A fast algorithm for OR-AND-OR synthesis

Design methods for OR-AND-OR three-level networks are useful for exploiting the flexibility of logic blocks in many complex programmable logic devices. This paper presents T RIMIN, a fast heuristic algorithm for designing OR-AND-OR networks from sum-of-products expressions. Each output of the network realizes a sum-of-complex-terms expression, where a complex term (CT) is similar to a product-of-sums expression. TRIMIN s objective is to lower the number of gates in the network. It first generates a set of CTs by applying factorization techniques; then, it solves a set-covering problem by using a greedy algorithm to select a subset of the CTs. The effectiveness of TRIMIN is demonstrated through experimental results.

Fast Boolean matching under permutation using representative

This paper presents an efficient method to check the equivalence of two Boolean functions under permutation of the variables. The problem is also known as Boolean matching. As a basis of the Boolean matching, we use the notion P-representative. If two functions have the same P-representative then they match. We develop a breadth-first search technique to quickly compute the P-representative. On an ordinary workstation, on the average, our method requires several microseconds to test the Boolean matching for functions with up to eight variables. This approach is promising for Boolean matching of multiplexor-based field-programmable gate arrays (FPGAs) and for library matching with many large cells.

An optimization of AND-OR-EXOR three-level networks

Presents a design method for AND-OR-EXOR three-level networks, where a single two-input EXOR gate is used. The network realizes an exclusive-OR of two sum-of-products expressions (EX-SOP), where the two sum-of-products expressions (SOPs) cannot share products. The problem is to minimize the total number of products in the two SOPs. We introduced the /spl mu/-equivalence of logic functions to develop minimization algorithms for EX-SOPs with up to five variables. We minimized all the representative functions of NP-equivalence classes for up to five variables and found that five-variable functions require up to nine products in minimum EX-SOPs. For n-variable functions, minimum EX-SOPs require at most 9/spl middot/2/sup n-5/ (n/spl ges/6) products. This upper bound is smaller than 2/sup n-1/, the upper bound for conventional SOPs.

GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions

A generalized Reed-Muller expression (GRM) is a type of AND-EXOR expressions. In a GRM, each variable may appear both complemented and uncomplemented. Networks realized using GRMs are easily tested. This paper presents GRMIN, a heuristic simplification algorithm for GRMs of multiple-output functions. GRMIN uses eight rules. As the primary objective, it reduces the number of products, and as the secondary objective, it reduces the number of literals. Experimental results show that, in most cases, GRMs require fewer products than conventional sum-of-products expressions (SOPs). GRMIN outperforms existing algorithms.

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EX-SOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzios AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMIN-like algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3 · 2n - 2 + 7n - 5 products in an EX-SOP while it is known that a sum-of-products expression (SOP) requires 6 · 2n - 4n - 5 products.

Subject independent agitation detection

The need to automate the detection of agitation for dementia patients is a major requirement for caregivers. This research aims at sensing and recognizing negative emotions specifically ldquostressrdquo for patients with dementia. An autonomous multi-sensory device has been developed to achieve automatic assessment of agitation and to control stimulation that will reduce the agitation level automatically. The focus of this paper is the agitation detection algorithm. Three vital signs are monitored for agitation detection: the Heart Rate (HR) the Galvanic Skin Response (GSR) and Skin Temperature (ST). These measures are fed into an SVM based learning machine. Results show accurate detection of agitation, quick adaptation to the subject and a strong correlation between the physiological signals monitored and the emotional states of the subjects. The result is a learning algorithm that is ldquoSubject-Independentrdquo.

Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions

This paper presents an exact minimization algorithm for fixed polarity Reed-Muller expressions (FPRMs) for incompletely specified functions. For an n-variable function with /spl alpha/ unspecified minterms there are 2/sup n+/spl alpha// distinct FPRMs. A minimum FPRM is one with the fewest products. The minimization algorithm is based on the multi-terminal binary decision diagrams. Experimental results for a set of functions are shown. The algorithm can be extended to obtain exact minimum Kronecker expressions for incompletely specified functions.