Debjit Sinha

Yield-Aware Cache Architectures

One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields have dropped to around 50% or less. This figure is expected to decrease even further in future technologies. To attack this growing problem, we develop four yield-aware micro architecture schemes for data caches. The first one is called yield-aware power-down (YAPD). YAPD turns off cache ways that cause delay violation and/or have excessive leakage. We also modify this approach to achieve better yields. This new method is called horizontal YAPD (H-YAPD), which turns off horizontal regions of the cache instead of ways. A third approach targets delay violation in data caches. Particularly, we develop a variable-latency cache architecture (VACA). VACA allows different load accesses to be completed with varying latencies. This is enabled by augmenting the functional units with special buffers that allow the dependants of a load operation to stall for a cycle if the load operation is delayed. As a result, if some accesses take longer than the predefined number of cycles, the execution can still be performed correctly, albeit with some performance degradation. A fourth scheme we devise is called the hybrid mechanism, which combines the YAPD and the VACA. As a result of these schemes, chips that may be tossed away due to parametric yield loss can be saved. Experimental results demonstrate that the yield losses can be reduced by 68.1% and 72.4% with YAPD and H-YAPD schemes and by 33.3% and 81.1% with VACA and Hybrid mechanisms, respectively, improving the overall yield to as much as 97.0%

Statistical gate sizing for timing yield optimization

Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely over-constrains the system and results in solutions with excessive penalties. Statistical timing analysis and optimization have consequently emerged as a refinement of the traditional static timing approach for circuit design optimization. In this paper, we propose a statistical gate sizing methodology for timing yield improvement. We build statistical models for gate delays from library characterizations at multiple process corners and operating conditions. Statistical timing analysis is performed, which drives gate sizing for timing yield optimization. Experimental results are reported for the ISCAS and MCNC benchmarks. In addition, we provide insight into statistical properties of gate delays for a given technology library which intuitively explains when and why statistical optimization improves over static timing optimization.

Advances in Computation of the Maximum of a Set of Gaussian Random Variables

This paper quantifies the approximation error when results obtained by Clark (1961) are employed to compute the maximum (max) of Gaussian random variables, which is a fundamental operation in statistical timing. We show that a finite lookup table can be used to store these errors. Based on the error computations, approaches to different orderings for pairwise max operations on a set of Gaussians are proposed. Experimental results show accuracy improvements in the computation of the max of multiple Gaussians, in comparison to the traditional approach. In addition, we present an approach to compute the tightness probabilities of Gaussian random variables with dynamic runtime-accuracy tradeoff options. We replace required numerical computations for their estimations by closed form expressions based on Taylor series expansion that involve table lookup and a few fundamental arithmetic operations. Experimental results demonstrate an average speedup of 2 using our approach for computing the maximum of two Gaussians, in comparison to the traditional approach, without any accuracy penalty.

Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment

The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce the bit-width precision of its computation units. This paper describes algorithms to optimize the bit widths of fixed-point variables for low power in a SystemC-based ASIC design environment. We propose an optimal bit-width allocation algorithm for two variables and a greedy heuristic that works for any number of variables. The algorithms are used in the automation of converting floating-point SystemC programs into ASIC synthesizable SystemC programs. Expected inputs are profiled to estimate errors in the finite precision conversions. Experimental results for the tradeoffs between quantization error, power consumption, and hardware resources used are reported on a set of four SystemC benchmarks that are mapped onto a 0.18-mum ASIC cell library from Artisan Components. We demonstrate that it is possible to reduce the power consumption by 50% on the average by allowing roundoff errors to increase from 0.5% to 1%

A unified framework for statistical timing analysis with coupling and multiple input switching

As technology scales to smaller dimensions, increasing process variations, coupling induced delay variations and multiple input switching effects make timing verification extremely challenging. In this paper, we establish a theoretical framework for statistical timing analysis with coupling and multiple input switching. We prove the convergence of our proposed iterative approach and discuss implementation issues under the assumption of a Gaussian distribution for the parameters of variation. A statistical timer based on our proposed approach is developed and experimental results are presented for the IS-CAS benchmarks. We juxtapose our timer with a single pass, non iterative statistical timer that does not consider the mutual dependence of coupling with timing and another statistical timer that handles coupling deterministically. Monte Carlo simulations reveal a distinct gain (up to 24%) in accuracy by our approach in comparison to the others mentioned.

Advances in Computation of the Maximum of a Set of Random Variables

This paper quantifies the approximation error in Clarks approach presented in C. E. Clark (1961) to computing the maximum (max) of Gaussian random variables; a fundamental operation in statistical timing. We show that a finite look up table can be used to store these errors. Based on the error computations, approaches to different orderings for pair-wise max operations on a set of Gaussians are proposed. Experiments show accuracy improvements in the computation of the max of multiple Gaussians by up to 50% in comparison to the traditional approach. To the best of our knowledge, this is the first work addressing the mentioned issues

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

This work presents a post-route, timing-constrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce crosstalk in deep sub-micron VLSI circuits. It is however critical to ensure that the timing constraints of the circuit are not violated after sizing. We present an iterative gate-sizing algorithm for crosstalk reduction based on Lagrangian relaxation that optimizes area and power while ensuring that the given timing constraints are met. Experimental results demonstrating the effectiveness of the algorithm are reported for the ISCAS benchmarks and other large circuits with comparisons to an alternative design methodology.

Statistical Timing Analysis With Coupling

As technology scales to smaller dimensions, increasing process variations and coupling induced delay variations make timing verification extremely challenging. In this paper, the authors establish a theoretical framework for statistical timing analysis with coupling. They prove the convergence of their proposed iterative approach and discuss implementation issues under the assumption of a Gaussian distribution for the parameters of variation. A statistical timer based on their proposed approach is developed and experimental results are presented for the International Symposium on Circuits and Systems benchmarks. They juxtapose their timer with a single pass, noniterative statistical timer that does not consider the mutual dependence of coupling with timing, and another statistical timer that handles coupling deterministically. Monte Carlo simulations reveal a distinct gain (up to 24%) in accuracy by their approach in comparison to the others mentioned

Driver waveform computation for timing analysis with multiple voltage threshold driver models

This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs formalize a class of gate models which include the existing industry standards, such as CCS and ECSM driver models as special cases. The analysis technique relies on primary MVTM characterization data and does not require explicit instantiation of controlled current source models. Therefore, the method is more accurate, efficient, and general than traditional transient analysis. The theoretical results are validated by detailed simulations and use within full chip timing analysis.

TAU 2013 variation aware timing analysis contest

Timing analysis is a key component of any integrated circuit (IC) chip design-closure flow, and is employed at various stages of the flow including pre/post-route timing optimization and timing signoff. While accurate timing analysis is important, the run-time of the analysis is equally critical with growing chip design sizes and complexity (for example, increasing number of clocks domains, voltage islands, etc.). In addition, the increasing significance of variability in the chip manufacturing process as well as environmental variability necessitates use of variation aware techniques (e.g. statistical, multi-corner) for chip timing analysis which significantly impacts the analysis run-time. The aim of the TAU 2013 variation aware timing contest is to seek novel ideas for fast variation aware timing analysis, by means of the following: (a) increase awareness of variation aware timing analysis and provide insight into some challenging aspects of the analysis, (b) encourage novel parallelization techniques (including multi-threading) for timing analysis, and (c) facilitate creation of a publicly available variation aware timing analysis framework and benchmarks to further advance research in this area.