Michael H. Wood

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system

The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm design, while still fitting within the same power envelope. Despite the many difficult engineering hurdles to be overcome, the design team was able to achieve a product frequency of 5.2GHz, providing a significant performance boost for the new system.

4.1 22nm Next-generation IBM System z microprocessor

The next-generation System z design introduces a new microprocessor chip (CP) and a system controller chip (SC) aimed at providing a substantial boost to maximum system capacity and performance compared to the previous zEC12 design in 32nm [1,2]. As shown in the die photo, the CP chip includes 8 high-frequency processor cores, 64MB of eDRAM L3 cache, interface IOs (“XBUS”) to connect to two other processor chips and the L4 cache chip, along with memory interfaces, 2 PCIe Gen3 interfaces, and an I/O bus controller (GX). The design is implemented on a 678 mm2 die with 4.0 billion transistors and 17 levels of metal interconnect in IBMs high-performance 22nm high-x CMOS SOI technology [3]. The SC chip is also a 678 mm2 die, with 7.1 billion transistors, running at half the clock frequency of the CP chip, in the same 22nm technology, but with 15 levels of metal. It provides 480 MB of eDRAM L4 cache, an increase of more than 2× from zEC12 [1,2], and contains an 18 MB eDRAM L4 directory, along with multi-processor cache control/coherency logic to manage inter-processor and system-level communications. Both the CP and SC chips incorporate significant logical, physical, and electrical design innovations.

Burn-in effectiveness-theory and measurement

Burn-in effectiveness is modeled as a function of time, temperature, electrical stress, stress coverage and failure mechanism. Actual field data for a variety of products is used to validate or deduce the relevant burn-in parameters. The modeling of burn-in is discussed to show the importance of the acceleration and stress coverage of the burn-in and of the failure distribution of the product. The modeling of burn-in is used to explain the failure characteristics of products which experience burn-in. The modeling of the characteristics of the failure distribution of burned-in product was used to analyze several experimental or reliability data sets to either validate or deduce the relevant parameter estimates for the specific burn-in. The modeling also extracts the relevant burn-in parameters from an analysis of field reliability performance.<<ETX>>

Evidence for an incubation time in electromigration phenomena

A large number of identical structures as well as many different structures were analyzed. The question of which distribution provides the best fit for electromigration failure is discussed. The possible choices of a distribution are extended, and it is shown that the inclusion of a third parameter, an incubation time, leads to the most successful fit. The use of an incubation time is explored for both the log-normal and Weibull distributions. A significant incubation time was found in all cases along with characteristic times that varied from lot to lot. In all of the structures examined there was not a compelling argument for selecting either distribution. The incubation time was found to be significant in every case and, unlike the median time to failure, does not vary among evaporations.<<ETX>>

Converting an SRAM from bulk Si to partially depleted SOI

The conversion of an existing standard cell compatible SRAM macro to a partially depleted SOI process is described. The issues discovered in the conversion were: changed coupling capacitance and noise analysis, history effects in the sense amplifier, setup and hold time analysis and thermal effects. For each of these effects the steps taken to meet functionality requirements are explained.

Burn-in Modeling - The Application Of Theory To Burn-in And Field Data

Sciniconductor chip reliability is commonly improved through burn-in. The theory of burn-in modcling and statistics is describcd and applicd to scvcral CRSC studies using actual field data. Analysis of ficld data validates or estimates the burn-in paramcters for each product.

Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains

This paper presents an approach to solving the problem of generating a single statistical timing macro-model or abstract for a chip component, and subsequently applying it smartly at multiple voltage domain conditions at a parent level of hierarchy during hierarchical timing. This approach avoids overheads in a traditional approach of having either multiple abstracts for the same component corresponding to different voltage domains, or having excessive guard-bands in a single common abstract. Results are presented for a set of test cases including industrial microprocessor units. The results exhibit more than 200 picoseconds of improved accuracy (both pessimism reduction and optimism avoidance) when using the proposed solution in comparison to an approach that assumes a single voltage domain compatible abstract.

Practical statistical static timing analysis with current source models

This paper considers the practical nuances of using current source gate models in an industrial statistical timing analysis environment. Specifically, the memory overhead of a naive implementation combining statistical and current source models to obtain and store gate output waveforms is found to be impractical for large microprocessor designs. A study is performed to observe variational gate output waveforms, and a technique is presented to store the waveforms in a memory efficient manner with minimal accuracy impact. The presented technique is validated over a set of 14 nanometer designs, and has enabled the usage of current source models in our industrial statistical timing analysis flow. Results demonstrate slack accuracy improvements of up to 17 picoseconds with a 1.15X run-time overhead and 1.1 gigabytes per million-gates memory overhead in comparison to an existing flow.