Deepak D. Sherlekar

N-channel and P-channel FINFET cell architecture

APPARATUSES AND METHODS FOR EFFICIENT POWER RAIL STRUCTURES FOR CELL LIBRARIES

N-channel and P-channel finFET cell architecture with inter-block insulator

N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH

Pin routing in standard cells

Various methods and apparatuses to route multiple power rails to a cell

Power Routing in Standard Cells

Cell Architecture for Increasing Transistor Size

Power Routing in Standard Cell Designs

FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE