Victor Moroz

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV)

Large thermal mismatch stress can be introduced in 3D-Integration structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. The TSV induced stress changes silicon mobility and ultimately alters device performance. The mobility and performance change differs in nand p- silicon and is a function of the distance to the TSV. In addition, the TSV induced stress acts on the barrier layer, the landing pad, the interconnects, and the dielectrics. The interactions with defects may lead to crack nucleation and growth, and compromise the structure reliability. Furthermore, the material choice that reduces silicon stress for less impact on performance may increase stresses in other regions where reliability is of concern. This paper studies these effects and their dependence on various integration configurations.

Exploring the limits of stress-enhanced hole mobility

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).

Layout impact on the performance of a locally strained PMOSFET

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L/sub s/d/) and the device width are further scaled. TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si1-xGex S/D) technology. Experimental results on Si1-xGex S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si1-xGex is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si1-x Gex and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si1-xGe x S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes

7-nm FinFET CMOS Design Enabled by Stress Engineering Using Si, Ge, and Sn

Bandgap and stress engineering using group IV materials-Si, Ge, and Sn, and their alloys are employed to design a FinFET-based CMOS solution for the 7-nm technology node and beyond. A detailed simulation study evaluating the performance of the proposed design is presented. Through the use of a common strain-relaxed buffer layer for p- and n-channel MOSFETs and a careful selection of source/drain stressor materials, the CMOS design is shown to achieve performance benefits over strained Si, meet the IOFF requirements, and provide a path for continued technology scaling.

Stress-Aware Design Methodology

Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This stress is generated by a variety of intentional and unintentional stress sources. Shallow trench isolation is an example of an unintentional stress source, whereas embedded SiGe in the source and drain is an example of an intentional stress source. The amount of stress in each transistor in the circuit depends on the shape of its diffusion area as well as the density of the adjacent layout. The resulting non-uniform stress distribution alters individual transistor performance and, ultimately, the behavior of the circuit. In this paper, several examples are used to illustrate this effect based on design rules for the 45 nm technology node. A number of alternative approaches are suggested for partially suppressing or completely eliminating the stress-induced performance variations

Optimizing boron junctions through point defect and stress engineering using carbon and germanium co-implants

We report the fabrication of p+∕n junctions using Ge+, C+, and B+ co-implantation and a spike anneal. The best junction exhibits a depth of 26nm, vertical abruptness of 3nm∕decade, and sheet resistance of 520Ohm∕square. The junction location is defined by where the boron concentration drops to 1018cm−3. These junctions are close to the International Technology Roadmap specifications for the 65nm technology node and are achieved by careful engineering of amorphization, stresses, and point defects. Advanced simulation of boron diffusion is used to understand and optimize the process window. The simulations show that the optimum process completely suppresses the transient-enhanced diffusion of boron and the formation of boron-interstitial clusters. This increases the boron solubility to 20% above the equilibrium solid-state solubility.

A systematic study of trade-offs in engineering a locally strained pMOSFET

We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman spectroscopy (/spl mu/RS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.