Deepak M. Mathew

Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs

Dynamic Random Access Memories (DRAM) have a big impact on performance and contribute significantly to the total power consumption in systems ranging from mobile devices to servers. Up to half of the power consumption of future high density DRAM devices will be caused by refresh commands. Moreover, not only the refresh rate does depend on the device capacity, but it strongly depends on the temperature as well. In case of 3D integration of MPSoCs with Wide I/O DRAMs the power density and thermal dissipation are increased dramatically. Hence, in 3D-DRAM even more DRAM refresh operations are required. To master these challenges, clever DRAM refresh strategies are mandatory either on hardware or on software level using new or already available infrastructures and implementations, such as Partial Array Self Refresh (PASR) or Temperature Compensated Self Refresh (TCSR). In this paper, we show that for dedicated applications refresh can be disabled completely without or with negligible impact on the application performance. This is possible if it is assured that either the lifetime of the data is shorter than the currently required DRAM refresh period or if the application can tolerate bit errors to some degree in a given time window.

Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM

In the context of approximate computing, Approximate Dynamic Random Access Memory (ADRAM) enables the tradeoff between energy efficiency, performance and reliability. The inherent error resilience of applications allows sacrificing data storage robustness and stability by lowering the refresh rate or disabling refresh in DRAMs completely. Consequently, it is important to know exactly the statistical DRAM behavior with respect to retention time, process variation and temperature to manage this trade-off and thereby deliberately exploiting the error resilience of different target applications.

Efficient reliability management in SoCs - an approximate DRAM perspective

In todays computing systems Dynamic Random Access Memories (DRAMs) have a large influence on performance and contribute significantly to the total power consumption. Thus, recent research activities bring the idea of approximate DRAM into focus to save power and improve performance by lowering the refresh rate or disabling refresh completely. Hence, fast and accurate models are required for a thoroughly exploration of approximate DRAM for error resilient applications. In this paper we present a holistic simulation environment for investigations on approximate DRAM and show the impact on error resilient applications.

A new bank sensitive DRAMPower model for efficient design space exploration

In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a large impact on performance and contribute a significant part to the total consumed power. Therefore, it is crucial to have an accurate DRAM power model for exhaustive design space explorations, which can handle different types of DRAM devices. In this paper, we present an improved version of the well known DRAMPower model. Our enhanced model is derived and calibrated from real measurements and outperforms pessimistic state-of-the-art DRAM power estimators like the widely used spread sheet provided by Micron.

A Platform to Analyze DDR3 DRAM’s Power and Retention Time

<italic>Editor’s note:</italic> The authors explore the intrinsic trade-off in a DRAM between the power consumption (due to refresh) and the reliability. Their unique platform allows tailoring to the design constraints depending on whether power consumption, performance or reliability has the highest design priority. <italic>—Jörg Henkel, Karlsruhe Institute of Technology</italic>

ConGen: An Application Specific DRAM Memory Controller Generator

The increasing gap between the bandwidth requirements of modern Systems on Chip (SoC) and the I/O data rate delivered by Dynamic Random Access Memory (DRAM), known as the Memory Wall, limits the performance of todays data-intensive applications. General purpose memory controllers use online scheduling techniques in order to increase the memory bandwidth. Due to a limited buffer depth they only have a local view on the executed application. However, numerous applications possess regular or fixed memory access patterns, which are not yet exploited to overcome the memory wall. In this paper, we present a holistic methodology to generate an Application Specific Memory Controller (ASMC), which has a global view on the application and utilizes application knowledge to decrease the energy and increase the bandwidth. To generate an ASMC we analyze the DRAM access pattern of the application offline and generate a custom address mapping by solving a combinatorial sequence partitioning problem.

A Bank-Wise DRAM Power Model for System Simulations

DRAM devices contribute significantly to the power consumption of todays computing systems. As the DRAM banks are getting denser, bank-wise power contribution is becoming more and more significant in modern DRAM devices. Therefore, DDR3 and LPDDR3/4 devices support Partial Array Self Refresh (PASR), while the latter and High Bandwidth Memory (HBM) provide additionally Per-Bank Refresh. To evaluate the benefits of these new sophisticated features in design space explorations, it is essential to have an accurate and fast Bank-Wise DRAM power model, which can be easily integrated into system level simulators. To the best of our knowledge, there exists no DRAM power model, which supports the aforementioned features. In this work, we present the fundamental equations for modeling bank-wise DRAM power. This model supports PASR and Per-Bank Refresh and is calibrated with measurements from various DRAM devices to improve the accuracy instead of using pessimistic datasheet values.

Using run-time reverse-engineering to optimize DRAM refresh

The overhead of DRAM refresh is increasing with each density generation. To help offset some of this overhead, JEDEC designed the modern Auto-Refresh command with a highly optimized architecture internal to the DRAM---an architecture that violates the timing rules external controllers must observe and obey during normal operation. Numerous refresh-reduction schemes manually refresh the DRAM row-by-row, eliminating unnecessary refreshes to improve both energy and performance of the DRAM. However, it has been shown that modern Auto-Refresh is incompatible with these schemes, that their manual refreshing of specified rows through explicit Activate and Precharge precludes them from exploiting the architectural optimizations available internally for Auto-Refresh operations. This paper shows that various DRAM timing parameters, which should be followed during normal DRAM operations can be reduced for performing Refresh operation, and by reverse engineering those internal timing parameters at system-init time an external memory controller can use them in conjunction with individual Activate and Precharge commands, thereby reducing the performance overhead afforded Auto-Refresh, while simultaneously supporting row-by-row refresh reduction schemes. Through physical experiments and measurement, we find that our optimized scheme reduces tRFC by up to 45% compared to the already highly-optimized Auto-Refresh mechanism. It is also 10% more energy-efficient and 50% more performance-efficient than the non-optimized row-by-row refresh. Further evaluations done by simulating future 16 Gb DDR4 devices show how the reduction in tRFC improves the application performance and energy efficiency. The proposed technique enhances all of the existing refresh-optimization schemes that use row-by-row refresh, and it does so without requiring any modification to the DRAM or DRAM protocol.