Dengwei Fu

A 400-MHz processor for the conversion of rectangular to polar coordinates in 0.25-/spl mu/m CMOS

This paper describes the architecture and IC implementation of a rectangular-to-polar coordinate converter for digital communication applications. The architecture core uses small lookup ROMs, fast multipliers, and a single angle-rotation stage. Area and latency are reduced in comparison with traditional methods. The processor, implemented in 0.25-/spl mu/m five-metal CMOS, has 14-b in-phase and quadrature channel inputs and 15-b magnitude and phase channel outputs. The phase and magnitude calculations have a maximum error of 0.00024 (0.0078% of /spl pi/) and 0.03 (1% of 2/spl radic/2), respectively. Computational latency is 19 cycles, and power dissipation is 470 mW at 2.5 V and 406 MHz (Mconversions/s).

A fast synchronizer for burst modems with simultaneous symbol timing and carrier phase estimations

In burst-mode data transmission used in GSM and IS-136, rapid acquisition of the symbol timing and the carrier phase from the observation of a short signal-segment is essential. Feedforward timing recovery is well suited for such transmissions due to its rapid acquisition characteristics. For personal mobile communications where low complexity and low power are the major requirements, it is desirable to sample the signal at the lowest possible rate and to have the synchronizer be as simple as possible. In this paper we propose a synchronizer for initial timing and carrier-phase estimation using preambles. The synchronizer needs just two samples per symbol period and it exhibits good performance, even for signals employing small excess bandwidth. These estimations can be obtained directly from the burst detector output. We also show that the synchronizer can be implemented very efficiently.

A 415 MHz direct digital quadrature modulator in 0.25-/spl mu/m CMOS

With a 32-bit frequency-control-word and two 15-bit (I and Q) data inputs, while employing less hardware than a conventional 2-multiplier/DDFS approach, this interleaved IC provides a quadrature DDFS (nearly for free!) with 100 dB spurious-free dynamic range and produces a 16-bit modulated sinusoidal output. Power dissipation is 0.5 W at an 830 MHz clock-rate with a 2.5 V supply.

Fixed-point analysis and realization of a blind beamforming algorithm

We present the fixed-point analysis and realization of a blind beamforming algorithm. This maximum-power beamforming algorithm consists of the computation of a correlation matrix and its dominant eigenvector, and we propose that the later be accomplished by the power method. After analyzing the numerical stability of the power method, we derive a division-free form of the algorithm. Based on a block-Toeplitz assumption, we design an FIR filter based system to realize both the correlation computation and the power method. Our ring processor, which is optimized to implement digital filters, is used as the core of the architecture. A special technique for dynamically switching filter inputs is shown to double the system throughput. Finally we discuss the issue of hardware/software hybrid realization.

An energy-efficient reconfigurable angle-rotator architecture

A reconfigurable angle rotator architecture is proposed and incorporated into an energy-efficient reconfigurable FFT/IFFT processor IC as its major computation component, endowing the FFT/IFFT processor with a significant scalable power dissipation feature with varying FFT size. The reconfigurability of the angle rotator is realized by dynamically allocating computation resources, which are subrotation stages in cascade. This approach tends to minimize the size of the lookup table while maintaining computation accuracy, and tends to minimize the area and power consumption while improving the overall performance.

A 400-MHz processor for the efficient conversion of rectangular to polar coordinates for digital communications applications

A 400-MHz digital rectangular-to-polar coordinate converter has been implemented in 0.25-/spl mu/m CMOS. The inputs to the chip are 14-bit in-phase and quadrature channels, and the outputs are 15-bit magnitude and phase channels. The phase and magnitude calculations have a maximum error of 0.00024 and 0.03, respectively. At a maximum frequency of 406 MHz, the circuit dissipates 470 mW of power at 2.5 V.

Optimal interpolator using a trigonometric polynomial

All-digital approaches for the adjustment of timing offset in digital modems have attracted increasing attention. We recently announced a novel interpolation method which, instead of approximating the continuous-time signal with a conventional polynomial and computing the synchronized samples using a Farrow structure, uses a trigonometric polynomial. Simulation results indicate that improved performance, reduced computational delay and, in most cases, simplified hardware can be achieved. To recover a synchronized sample from existing samples, given a timing offset, we show here that we can optimize this method such that the interpolation error in the recovered sample is minimized for that specific timing offset value. Using this optimization technique, the overall interpolation error is reduced. As for the implementation, the optimal interpolator does not require additional hardware as compared to our original method.