Alan N. Willson

Application of filter sharpening to cascaded integrator-comb decimation filters

A new architecture for the implementation of high-order decimation filters is described. It combines the cascaded integrator-comb (CIC) multirate filter structure with filter sharpening techniques to improve the filters passband response. This allows the first-stage CIC decimation filter to be followed by a fixed-coefficient second-stage filter, rather than a programmable filter, thereby achieving a significant hardware reduction over existing approaches. Furthermore, the use of fixed-coefficient filters in place of programmable-coefficient filters improves the overall throughput rate. The resulting architecture is well suited for single-chip VLSI implementation with very high data-sample rates. We discuss an example with specifications suitable for use in a wideband satellite communication subband tuner system and for signal analysis.

Median filters with adaptive length

Two algorithms using adaptive-length median filters are proposed for improving impulse-noise-removal performance for image processing. The algorithms can achieve significantly better image quality than regular (fixed-length) median filters when the images are corrupted by impulse noise. One of the algorithms, when realized in hardware, requires rather simple additional circuitry. Both algorithms can easily be integrated into efficient hardware realizations for median filters. The performance of the proposed filters is compared with regular median filters, generalized mean filters, and nonlinear mean filters. The hardware complexities of the filters are also compared. >

A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range

This paper describes the architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC). It is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 1.0-/spl mu/m CMOS, and tested. The IC produces 16-b sine and cosine outputs with a spurious-free dynamic range of more than 100 dBc. A 36-b frequency control word gives a tuning resolution of 0.0015 Hz at a 100-MHz sampling rate.

How to identify unstable DC operating points

The stability of operating points that satisfy the circuits DC operations but are nonetheless unobservable operating points is examined in a rigorous way. Two classes of DC operating points, unstable and potentially stable, are defined, and simple criteria, based only on the circuits DC equations, that can classify a given operating points stability are given. It is also shown that it suffices to model stray capacitance and inductance in only certain specific locations, for any given physical circuit, to correctly assess the stability of its operating point in the presence of a profusion of parasitic reactances. >

A theory and an algorithm for analog circuit fault diagnosis

A theory for the study of the analog circuit fault diagnosis problem is developed. Sufficient conditions are presented such that the value of each of the network elements is uniquely determinable from the networks behavior as seen from its external terminals. It is shown how one can determine-considering only the circuits topology-whether or not it is possible to compute the element values of a resistive network from the test-terminal measurements, before going through the process of actually attempting to solve for element values. The implications of the results are discussed when applied to networks containing solid-state devices such as diodes and transistors. Finally, an algorithm for the actual computation of the element values is proposed and its global convergence is proved. Furthermore, several examples are included to illustrate the applications of the theory developed in this paper.

A programmable FIR digital filter using CSD coefficients

An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-/spl mu/m CMOS technology.

Some aspects of the theory of nonlinear networks

In the development of network theory over the years, the primary focus of attention has been in the area of linear systems. Several reasons for this emphasis can easily be cited, but perhaps the foremost reason is that it has long been thought that, except in certain very special cases, little progress toward a rigorous definitive theory could be expected once the hypothesis of linearity is discarded. The recent success in the use of numerical methods for computing solutions of the equations for specific nonlinear networks (the importance of which is not to be minimized) has, furthermore, resulted in a certain complacency on the part of many engineers who occasionally need to solve network problems. One senses their outlook as being, basically, that whenever a particular nonlinear problem arises, one need only then run, data in hand, to the computer. Somewhat ironically, however, the development of computer-aided network analysis techniques has also been a prime impetus for many of the recent theoretical investigations in the field of nonlinear networks, and although much remains to be done, a rather comprehensive body of knowledge in this area has begun to take form. A number of related recent contributions to the theory of non-linear networks are reviewed here. As distinct from the computational aspects of the network analysis problem, we discuss work whose primary purpose is to yield an understanding of the nature of the equations that describe the behavior of nonlinear networks, and to identify and relate certain properties of the network elements, and the manner of their interconnection, to properties of the equations and their solutions. In addition, we do frequently touch on the problem of computation since, as has already been implied, it is indeed one of the purposes of the work discussed here to provide more of a theoretical foundation on which to base the numerical analyses.

A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring

A single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture is presented. Multi-level reconfigurability is realized by dynamically allocating computation resources needed by specific applications. The processor IC was fabricated in 0.25-/spl mu/m CMOS. It performs 8-point to 4096-point complex FFT/IFFT with power-consumption scalability and provides useful trade-offs between algorithm flexibility, implementation complexity and energy efficiency.

Insights into digital filters made as the sum of two allpass functions

The exact equivalence of the response of a resistance terminated lossless analog lattice filter to that of the algebraic sum of two allpass functions is discussed, culminating in a theorem giving simple necessary and sufficient conditions for a transfer function to be realized in this way. It is shown how various basic analog circuit relationships and properties possess direct counterparts in the realm of digital filtering. The importance of using the well-known characteristic function of analog filter theory for designing digital filters as the sum or difference of two allpass functions is emphasized. >

A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion

A phase-noise reduction technique for quadrature VCOs reduces and shapes the transistor thermal noise injected into the system, and also provides a phase-to-amplitude noise conversion mechanism to further reduce phase noise. Two experimental designs provide 17% and 1% tuning ranges centered at 5.1GHz and 5.3GHz with phase noise of -132.6dBc/Hz and -134.4dBc/Hz at a 1MHz offset, respectively