Dennis Buss

Experimental characterization of transfer Efficiency in charge-coupled devices

The most important characteristic of a charge-coupled device is its charge transfer efficiency (CTE). There are three basic types of loss which degrade CTE: fixed loss, proportional loss, and nonlinear loss. Examples are given of each type of loss and techniques for measurement of all three types of loss are described. A method of determining the minimum fat zero which eliminates fixed loss is shown and an experiment is presented which confirms that fixed loss due to surface states can be completely eliminated by the use of a fat zero. The effect of interelectrode gaps on CTE is discussed in detail. A nonlinear loss model is used to describe the dispersion due to barriers in the gaps and the very detrimental effect of wells in the gap region is shown. The techniques presented in the analysis of these losses are very general and can be used whenever a detailed description of the transfer loss mechanism is required.

Technology in the internet age

Internet electronic products have requirements different from those of personal computers (PCs). The increasing importance of Internet electronics is driving changes in development of IC technology. One important characteristic of the Internet Age is computational disaggregation. Whereas, over the past 20 years, PCs have been characterized by ever-increasing computation capabilities, emerging Internet electronic products are characterized by sufficient computation to achieve the function in a small, often portable, form factor. The imperative for lower cost, which enables penetration into mass markets, is a second area where Internet electronic products differ from PCs. Disaggregation and cost requirements are driving an unprecedented degree of system-on-a-chip (SoC) integration. In the Internet Age, SoC integration means more than integrating different digital cores. It also means integrating functions that are realized today in different technologies: logic, memory, analog, power management, passives and radio or wireline driver, depending on the product. Because SoC integration is motivated primarily by cost, diverse functions must be integrated together in standard CMOS with minimal cost addition. Cost-effective embedded memory technology also needs to be developed. Current examples of SoC integration include cell phones, cable/DSL modems, and Internet audio. These representative examples, together with others, are driving changes in the way ICs are developed. In the latter half of the decade, it is likely that SoC integration will expand to include MEMS, microphotonics, and on-chip energy sources. Moores Law scaling will continue at least through the end of this decade, but SoC integration will become an increasingly important technology imperative for continued cost reduction throughout the Internet Age.

SOC CMOS technology for personal Internet products

Worldwide demand for Personal Internet Products is increasing rapidly, and will shape the directions of CMOS technology in the years ahead. Personal Internet Products are loosely defined in this paper as communication, computing and consumer products, which are enabled by the Internet: cell phones, PDAs, WLANs, Internet audio/video, ADSL, cable modems etc. Personal Internet Products are based on Digital Signal Processing (DSP) and analog functionality. They are made accessible to billions of people around the globe by intense focus on cost through SOC integration. In the Internet Age, Moores Law will continue to be a technology imperative for the semiconductor industry. But SOC integration will be an additional technology imperative that drives down the cost of Personal Internet Product to mass market levels. SOC integration for Personal Internet Products requires the integration of analog, power analog, RF and memory onto the digital baseband processor, which is fabricated in high density, high performance, low cost digital CMOS technology. This paper describes the challenges and some of the solutions to achieve this vision.

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (VT) variation, already a significant issue in todays advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local VT variation and achieve a reliable design with minimal pessimism.

A 500-stage CCD transversal filter for spectral analysis

The operation and design of 500-stage charge-coupled device (CCD) transversal filters are described. The filters have been mask programmed for implementing two spectral analysis techniques: 1) bandpass filtering and 2) Fourier analysis using the chirp z transform (CZT) algorithm. The bandpass filter has a measured fractional 3 dB bandwidth of 0.0108 and 38 dB sidelobe rejection. The dynamic range is 75 dB with less than 45 dB total harmonic distortion. A sliding transform is defined which is useful for calculations of the power spectral density and is shown to be particularly advantageous in a CCD-CZT implementation. Using the sliding transform, a 500-point spectrum is calculated using CCDs with resolutions which can be varied from 1-200 Hz. The dynamic range of the power spectral output was measured to be 80 dB. A discussion is given of the performance limitation of a general CCD filter due to the inherent characteristics of the device. The results are evaluated for the 500-stage devices described above and indicate that sample rates from 25 Hz to 10 MHz are possible with a dynamic range approaching 100 dB while retaining high linearity.

CCD memory options

Implementation of Al-Al 2 O 3 -Al metalization, experimental performance of diverse CCDs, and a novel two-phase concept will be presented, within a discussion of the organization and fabrication tradeoffs for analog and digital memories, citing predicted impact.

Cellular handset integration -- SIP vs. SOC

Cellular handsets are rapidly evolving from voice-only products to highly featured designs featuring color displays, games, audio, video, cameras, Bluetooth, GPS, WLAN, highspeed wide-area data services, and other advanced features. This remarkable expansion in capability, in conjunction with ongoing customer demands for sleek, ergonomic, and reasonably priced handsets with good battery life, places considerable pressure on handset component providers to aggressively integrate the handset electronics. System-in-package (SIP) integration and system-on-chip (SOC) integration are two possible approaches. This paper investigates the tradeoffs between SIP and SOC integration for the integration of memories, analog, and RF electronics in the handset.

Far I.R. determination of the transverse optic lattice mode in PbTe at low temperature

Abstract The TO lattice mode of PbTe has been observed at low temperatures in the far infrared. Bulk reflectance measurements give a value of ωTO = 18.0 ± 1.0 cm-1. This low value is confirmed by magnetoptical reflectivity and transmission measurements in fields up to 90 kG.

On the ferroelectric nature of the cubic-rhombohedral phase transition in Pb1−xGexTe

Abstract Capacitance measurements at various fixed d.c. biases as a function of temperature are presented for junction diodes fabricated from alloys of Pb1−xGex with x=0.03, x=0.45 and x=0.06. Strong capacitance maxima at the temperatures associated with a cubic-rhombohedral phase transition are observed. These peaks are the first reported direct evidence for the ferroelectric nature of the crystalline phase transition in the PbTe based alloys.

Cellular handset integration - SIP versus SOC

Cellular handsets are rapidly evolving from voice-only products to highly featured designs featuring color displays, games, audio, video, cameras, Bluetooth, GPS, WLAN, high-speed wide-area data services, and other advanced features. This remarkable expansion in capability, in conjunction with ongoing customer demands for sleek, ergonomic, and reasonably priced handsets with good battery life, places considerable pressure on handset component providers to aggressively integrate the handset electronics. System-in-Package (SIP) integration and System-on-Chip (SOC) integration are two possible approaches. This paper investigates the tradeoffs between SIP and SOC integration for the integration of memories, analog, and RF electronics in the handset.