Rahul Rithe

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (VT) variation, already a significant issue in todays advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local VT variation and achieve a reliable design with minimal pessimism.

The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage

In order to achieve ultra-low power (ULP), ICs are being designed for VDD ≤ 0.5 V. At these low voltages, random dopant fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the global corner delay. Moreover, the probability density function (PDF) of this stochastic delay can be highly non-Gaussian. In order to predict the statistical impact of RDF-induced local variations on logic timing, it is necessary to incorporate these effects into a timing closure methodology. This paper presents a computationally efficient methodology for stochastic characterization of standard cell li- braries at low voltage, where the cell delay is a nonlinear function of the transistor random variables (RVs), and the resulting cell delay has a non-Gaussian PDF. It also presents a computation- ally efficient methodology for computing any point on the PDF of a timing path (TP) delay, in the case where cell delays are non-Gaussian. The method is called nonlinear operating point analysis of local variation (NLOPALV). The general NLOPALV theory is developed. It is applied to cell library characterization, and the accuracy of the NLOPALV approach is validated by comparison to Monte Carlo simulation. NLOPALV is also applied to timing path analysis on a 28 nm DSP IC. The approach has been implemented using commercial CAD tools, and integrated into a commercial IC design flow. The NLOPALV approach gives timing results that are within 5% accuracy compared to Monte Carlo analysis at VDD = 0.5 V. This compares to errors on the order of 50% when the Gaussian approximation is used.

Non-linear operating point statistical analysis for local variations in logic timing at low voltage

For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ≤ 0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Increasing number of energy-limited applications continue to drive the demand for designing systems with high energy efficiency. This tutorial covers the main building blocks of a system implementation including digital logic, embedded memories, and analog-to-digital converters and describes the challenges and solutions to designing these blocks for low-voltage operation.

Reconfigurable processor for energy-scalable computational photography

Computational photography applications, such as lightfield photography [1], enable capture and synthesis of images that could not be captured with a traditional camera. Non-linear filtering techniques like bilateral filtering [2] form a significant part of computational photography. These techniques have a wide range of applications, including High-Dynamic Range (HDR) imaging [3], Low-Light Enhanced (LLE) imaging [4], tone management and video enhancement. The high computational complexity of such multimedia processing applications necessitates fast hardware implementations [5] to enable real-time processing. This paper describes a hardware implementation of a reconfigurable multi-application processor for computational photography.

Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations

When CMOS is operated at a supply voltage of 0.5V and below, Random Do pant Fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the nominal delay. Moreover, the Probability Density Function (PDF) of this stochastic delay can be highly non-Gaussian. The Non-Linear, Operating Point Analysis of Local Variations (NLOPALV) technique has been shown to be accurate and computationally efficient in simulating any point on the delay PDF of a logic Timing Path (TP). This paper applies the NLOPALV approach to characterizing the stochastic delay of logic cells. NLOPALV theory is presented, and NLOPALV is used to characterize a cell library designed in 28 nm CMOS. NLOPALV is accurate to within 5% compared to SPICE-based Monte Carlo analysis.

Quad Full-HD transform engine for dual-standard low-power video coding

Transform engine is a critical part of the video codec and increased coding efficiency often comes at the cost of increased complexity in the transform module. H.264/AVC and VC-1 are two recent video coding standards that employ variable size and hierarchical transforms to achieve coding efficiency. In this work we propose a shared-reconfigurable transform engine using the structural similarity and symmetry of the transforms for H.264/AVC and VC-1. An approach to eliminate the need for an explicit transpose memory in 2D transforms is proposed. Data dependency is exploited to reduce power consumption. Ten different versions of the transform engine, such as with and without hardware sharing, with and without transpose memory, are implemented in the design. The design is fabricated using commercial 45nm CMOS technology and all implemented versions are verified. The shared-reconfigurable transform engine without transpose memory supports Quad Full-HD (3840 × 2160) video encoding at 30fps, while operating at 0.52V, with measured power of 214μW. Hardware sharing saves 30% area compared to individual H.264 and VC-1 implementations combined. Eliminating an explicit transpose memory using a 2D (8×8) output buffer reduces area by 23% and power by 26%. Several of ideas proposed here can potentially be extended to future video coding standards such as HEVC.

Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding

Transform engine is a critical part of the video codec, and increased coding efficiency often comes at the cost of increased complexity in the transform module. In this work, we propose a shared transform engine for H.264/AVC and VC-1 video coding standards, using the structural similarity and symmetry of the transforms. An approach to eliminate an explicit transpose memory in 2-D transforms is proposed. Data dependency is exploited to reduce power consumption. Ten different versions of the transform engine, such as with and without hardware sharing and with and without transpose memory, are implemented in the design. The design is fabricated using commercial 45-nm CMOS technology, and all implemented versions are verified. The shared transform engine without transpose memory supports Quad Full-HD (3840 × 2160) video encoding at 30 fps, while operating at 0.52 V, with a measured power of 214 μ W. This highly scalable design is able to support 1080 p at 30 fps, while operating down to 0.41 V, with measured power of 79 μW and 720 p at 30 fps, while operating down to 0.35 V, with measured power of 43 μW. Hardware sharing saves 30% area compared with individual H.264 and VC-1 implementations combined. Eliminating an explicit transpose memory using a 2-D (8 × 8) output buffer reduces area by 23% and power by 26%. Ideas proposed here can potentially be extended to future video coding standards such as HEVC.

Correction to “Reconfigurable Processor for Energy-Efficient Computational Photography” [Nov 13 2908-2919]

Manuscript received August 17, 2014; accepted August 23, 2014. Date of publication September 16, 2014; date of current version October 24, 2014. R. Rithe, P. Raina, N. Ickes, and A. P. Chandrakasan are with the Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail: rjrithe@mtl.mit.edu). S. V. Tenneti is with the California Institute of Technology, Pasadena, CA 91106 USA. Digital Object Identifier 10.1109/JSSC.2014.2353797 verified to be operational from 25 MHz at 0.5 V to 98 MHz at 0.9 V with SRAMs operating at 0.9 V.” The processor and the SRAMs were connected together and operated from the same supply voltage on chip. As a result, this statement should be modified as: “The test chip, shown in Fig. 19, is implemented in 40 nm CMOS technology and verified to be operational from 25 MHz at 0.5 V to 98 MHz at 0.9 V.” The reference to the SRAM supply being at 0.9 V should be ignored in the table in Fig. 19. We would like to thank our colleagues Arun Paidimarri and Mehul Tikekar for bringing this error to our attention.