Dennis McCain

Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes

We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and utilize the properties of the min approximation to significantly reduce the memory requirement. The proposed architecture is suitable for mobile devices with data-rates of tens of mbps

Initial Synchronization for 802.16e Downlink

In this paper, we propose an initial synchronization scheme for time and carrier frequency synchronization and cell identification in 802.16e OFDMA downlink. The proposed method does not require knowledge of actual transmitted preamble, but only utilizes the preamble structure and inverse Fourier transform properties to obtain time/frequency synchronization. Through simulations, we show that the proposed synchronization method is suitable in multipath as well as multicell environment. Although evaluated for IEEE 802.16e, the proposed method can also be used in other OFDM systems with similar signal properties.

Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study

We present an efficient LMMSE chip equalizer to suppress the interference caused by the multipath fading channel in the MIMO multi-code CDMA downlink. The block-Toeplitz structure in the correlation matrix is approximated with a block circulant matrix. An FFT-based algorithm is applied to avoid the direct-matrix-inverse (DMI) in the system equation. Hermitian optimization is proposed to further reduce the complexity. A comparative study in both performance and complexity with the conjugate-gradient (CG) algorithm is then presented. The simulation shows very promising results for the FFT-based equalizer compared with both the DMI and CG algorithms.

Scalable FPGA architectures for LMMSE-based SIMO chip equalizer in HSDPA downlink

In this paper, scalable FPGA architectures for the LMMSE-based chip-level equalizer in HSDPA downlink receivers are studied. An FFT-based algorithm is applied to avoid the direct matrix inverse by utilizing the block-Toeplitz structure of the correlation matrix. A pipelined-multiplexing-scheduler (PMS) is designed in the front-end to achieve scalable computation of the correlation coefficients. Very efficient VLSI architectures are designed by investigating the multiple level parallelism and pipelining with a precision-C based high-level-synthesis (HLS) design methodology. A 1/spl times/2 single-input-multiple-output (SIMO) downlink receiver is designed and integrated in the HSDPA prototype system with Xilinx Virtex-II XC2V6000 FPGAs. The design demonstrates more area/time efficiency by achieving the best tradeoffs between the usage of functional units and real-time requirements.

Rapid scheduling of efficient VLSI architectures for next-generation HSDPA wireless system using Precision C synthesizer

In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures are scheduled rapidly with specific hardware resource/ timing/architecture constraints from C/C++ level modeling by allocating the usage of functional units and real-time requirements. Using this methodology, a system-on-chip architecture for the next-generation CDMA system, i.e., HSDPA system, is prototyped rapidly. Advanced algorithms including chip-level equalizer, turbo codec and clock tracking, frequency offset compensation, are scheduled with Precesion C. A relatively more area/timing efficient RTL architecture is generated automatically and integrated with other design blocks in HDL designer, then implemented efficiently in Xilinx FPGAs. This new design flow demonstrates productivity improvement of 2X for typical wireless communication algorithms and reduces the risk of product development dramatically.

An efficient circulant MIMO equalizer for CDMA downlink: algorithm and VLSI architecture

We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI) of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

Reduced QRD-M detector in MIMO-OFDM systems with partial and embedded sorting

In this paper, we present a reduced QRD-M matrix symbol detector in MIMO-OFDM systems. The QRD-M algorithm first decomposes the MIMO channel matrix into upper triangular matrix and applies a limited tree search to approximate the maximum-likelihood detector. The metric update is reduced from O(4.5 MC) to O(1.5 MC) by extracting the commonality. We then propose a partial quick-sort procedure and an embedded insert sort to achieve almost linear sorting. In the second part, we present efficient VLSI architectures utilizing the parallelism between subcarriers and design the pipelining in the multi-stage MIMO processing. The real-time architecture is implemented in an FPGA-based hardware accelerator with compact form factor, which achieves up to 100/spl times/ speedup in the simulation time.

Matlab as a development environment for FPGA design

In this paper we discuss an efficient design flow from Matlab/spl reg/ to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algorithm development to implementation. We show that integrating Matlab with HDL design tools such as HDL designer/spl reg/ and Precision-C/spl reg/, an efficient design flow, suitable for rapid prototyping, can be obtained. The design flow accelerates process of algorithm development and simplifies test-bench formulation and verification process. The overall development time thus can be significantly reduced. We elaborate on the advantages and disadvantages of the design flow. It will be shown that Matlab based design flow generates functional specifications that are useful for RTL development.

Compact hardware accelerator for functional verification and rapid prototyping of 4G wireless communication systems

In this paper, we propose an FPGA-based hardware accelerator platform with Xilinx Virtex-II V3000 in a compact PCMCIA form factor. By partitioning the complex algorithms in the 4G simulator to the hardware accelerator, we apply an efficient Catapult-C methodology to quickly evaluate the area/speed tradeoffs and rapidly schedule synthesizable RTL models for implementation. The simulation time is accelerated by 100/spl times/ for a QRD-M algorithm. This not only enables much faster verification in the 4G standard environment, but also provides software/hardware codesign and rapid prototyping of the core algorithm in a realistic fixed-point platform.

Rapid prototyping and VLSI exploration for 3g/4G MIMO wireless systems using integrated catapult-c methodology

In this paper, we present an un-timed Catapult C/C++ based methodology that integrates key technologies for high-level VLSI modelling of 3G/4G wireless systems to enable extensive time/area tradeoff study. Case study is given to explore the VLSI design space for various computational intensive algorithms in both MIMO-CDMA and MIMO-OFDM systems. The prototyping experience demonstrates significantly improved architecture efficiency and productivity