Tejas Bhatt

Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes

We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and utilize the properties of the min approximation to significantly reduce the memory requirement. The proposed architecture is suitable for mobile devices with data-rates of tens of mbps

Efficient linear equalization for high data rate downlink CDMA signaling

In this paper, we propose an FFT-based linear equalization algorithm for the CDMA downlink. By approximating the correlation matrix with a circulant matrix, which is diagonalized by the DFT matrix, we are able to incorporate the efficient FFT operations and avoid the direct matrix inversion. Furthermore, we show that with the help of Kronecker algebra and the notion of dimension-wise and element-wise FFT, we are able to extend the FFT-based method to cases where multi-channel diversity, such as over-sampling or receive antenna array diversity, is present. Numerical simulations show that the FFT-based algorithm overlaps with the direct matrix inversion method for most of the low to medium SNR range and have a small loss at high SNR.

Initial Synchronization for 802.16e Downlink

In this paper, we propose an initial synchronization scheme for time and carrier frequency synchronization and cell identification in 802.16e OFDMA downlink. The proposed method does not require knowledge of actual transmitted preamble, but only utilizes the preamble structure and inverse Fourier transform properties to obtain time/frequency synchronization. Through simulations, we show that the proposed synchronization method is suitable in multipath as well as multicell environment. Although evaluated for IEEE 802.16e, the proposed method can also be used in other OFDM systems with similar signal properties.

Reconfigurable Shuffle Network Design in LDPC Decoders

Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurability was seldom studied. In most of the published work, the shuffle network between the log-likelihood ratio (LLR) memory and the check- node units (CNU) is predetermined and optimized for a specific code. However, the most of the modern wireless communication systems typically specify multiple code-rates, codeword lengths and sub-matrix sizes (for the QC-LDPC codes) to provide and guarantee quality-of-service (QoS) over challenging channel conditions. It is therefore desirable to define a reconfigurable decoder architecture that can support different parameters. This paper proposes an adaptive shuffling algorithm for QC-LDPC codes which together with the Benes network provides arbitrary cyclic shift for arbitrary submatrix size smaller than the input size of the Benes network. For the submatrix size larger than the Benes network input size, the proposed algorithm can be extended to obtain the cyclic shift in multiple stages. Compared with the direct implementation of m m-to-1 multiplexers, the proposed algorithm achieves significant savings on area and routing complexity.

Matlab as a development environment for FPGA design

In this paper we discuss an efficient design flow from Matlab/spl reg/ to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algorithm development to implementation. We show that integrating Matlab with HDL design tools such as HDL designer/spl reg/ and Precision-C/spl reg/, an efficient design flow, suitable for rapid prototyping, can be obtained. The design flow accelerates process of algorithm development and simplifies test-bench formulation and verification process. The overall development time thus can be significantly reduced. We elaborate on the advantages and disadvantages of the design flow. It will be shown that Matlab based design flow generates functional specifications that are useful for RTL development.

Modified Min-Sum Algorithm for LDPC Decoders in UWB Communications

Several variations of the sum-product algorithm (SPA) have been proposed for the decoding of the low density parity check (LDPC) codes. Among these, the log domain belief propagation algorithm (log-BPA or simply BPA) is widely adopted in most of the proposed LDPC decoder architectures. The check node unit (CNU), which computes the check-to-variable (C2V) messages, is computationally the most complex part of the decoder employing the belief propagation algorithm. The BPA can be approximated using a sub-optimal min-sum algorithm; however, it suffers from the performance loss. The min-sum algorithm can be easily implemented with comparators and multiplexers, thereby reducing the area and the power consumption of the decoder, critical for the high data-rate applications such as ultra wide-band (UWB) communications system. Due to the performance degradation, the decoder needs to perform more decoding iterations to reach the desired performance. This, in turn, increases the decoder latency and reduces the decoder throughput. One approach to improve the decoder throughput is to layout more parallel CNUs inside a decoder, but this offsets the advantage of the min-sum implementation. On the other hand, the performance of the min-sum algorithm can be improved by scaling the node-to-check messages and it is possible to find optimal scaling factor for a given channel. In this paper, we propose an improvement to the min-sum algorithm based on the analysis of the error term in the min-sum algorithm. The proposed algorithm achieves the performance similar to the scaled min-sum (SMS) approach with optimal scaling, in the additive white Gaussian noise (AWGN) channel. We also show min-sum utilized with different fading channels and LDPC codes without any further adjustments. Thus, the proposed MMS algorithm provides flexibility in real applications, which need to support multiple code rates, block sizes and have to operate in unknown fading channels. The performance of the proposed algorithm is evaluated for the MB-OFDM UWB systems with short distance indoor channel models. To meet the speed requirement of the of the UWB systems, a bit-level pipelined comparator is developed, which significantly reduces the latency of the critical path in the comparison circuit

Performance Analysis of the Structured Irregular LDPC Coded MIMO-OFDM System with Iterative Channel Estimator

In this paper, we evaluate the performance of the receiver employing an iterative RLS-based data detection and channel estimation for the structured irregular LDPC coded MIMO-OFDM system. Using the EXIT chart analysis, the performance of the detector with various approximate decoding algorithms is analyzed

Performance analysis of the detector for structured irregular LDPC coded MIMO-OFDM system

In this paper, we evaluate the performance of the MIMO data detector with various decoding architectures in the structured irregular LDPC coded MIMO-OFDM system. Using the EXIT chart analysis, the performance of the data detector in the iterative MIMO-OFDM system with various approximate decoding algorithms is analyzed.

Structured Interleavers and Decoder Architectures for Zigzag Codes

We propose structured interleaver design for parallel concatenated Zigzag codes. While the proposed design performs as good as or better than random interleavers for various block-sizes, it improves the error floor of the Zigzag codes and offers a lot of parallelism suitable for high data-rate applications. The interleaver can be specified with only a few parameters and can be efficiently implemented in both hardware and software. We also evaluate semi-parallel Zigzag decoder architecture that exploits the parallelism of the proposed interleavers to improve the throughput. We also evaluate the performance of an efficient decoding schedule for semi-parallel Zigzag decoder that provides better throughput and performance trade-offs compared to the fully parallel and serial decoder schedule. The proposed interleaver scheme and architecture are suitable for high throughput Ultra Wideband communications that demand data-rates up to several hundred mbps.

Iterative Extended Soft-RLS Algorithm for Joint Channel and Frequency Offset Estimation for Coded MIMO-OFDM Systems

In this paper, we propose an iterative extended soft- RLS (IES-RLS) algorithm for a joint channel and frequency offset estimation for the coded MIMO-OFDM system. In this system, the a posteriori probability for the information bit computed from the channel decoder is used in the MIMO data detector, whose coded soft symbol decision is used in the proposed IES-RLS algorithm. To develop a feasible algorithm, the first order linearization with respect to channel parameters is used. Performance of the IES-RLS algorithm is verified with the Turbo and irregular LDPC codes.