Derek Hummerston

An 18 b 12.5 MS/s ADC With 93 dB SNR

This paper presents a precision 18-bit 12.5 MS/s ADC that was designed primarily for digital X-ray imaging systems. This ADC was intended to have a faster output data rate than the precision successive approximation ADCs normally chosen for these systems but with similar DC accuracy and dynamic range. The chosen architecture consists of a pipeline of two multi-bit successive approximation converters. The first successive approximation ADC generates an initial coarse conversion result. The DACs within this converter are then used to generate a residue which is amplified by a residue amplifier before being converted by a second successive approximation ADC. Four comparators within each ADC allow 2 bits to be determined each bit trial. Capacitor mismatch errors are digitally corrected with error coefficients stored in non-volatile memory. Dither is used to reduce the effect of errors in the flash ADC within the second ADC. The ADC was implemented on 0.25 m CMOS process with PIP capacitors and achieves a SNR of 93 dB with a 50 kHz input tone. INL and DNL are within LSB and LSB respectively. Power consumption is 105 mW, excluding LVDS interface power.

An 18b 12.5MHz ADC with 93dB SNR

This ADC is aimed at medical imaging such as digital x-ray where multiple channels from a photodiode array are multiplexed to a number of ADCs. These ADCs need to have a dynamic range in excess of 90dB to cater for the distance and composition of tissues that the x-rays have passed through. INL matching between converters of about 1 LSB at the 16b level is also required to avoid visible artifacts across pixel boundaries. These INL and dynamic range specifications are met by a number of commercially available 16b successive approximation (SA) ADCs but none at conversion rates more than 4 MHz. Conversion rate can be increased by determining 2 or more bits per bit trial by using a low resolution flash within a SA ADC. In [1] the residue amplifier (RA) that drives the inputs of the flash converter is within the SA loop. Sufficient time must be allowed for this RA to settle to the required accuracy each bit trial. [2] has no gain between the SA DACs and the flash and so avoids any RA settling delays. However to avoid upsetting the SA algorithm, the flash comparator errors must remain smaller than the size of each trial space. As a result this latter approach has so far been limited to low to medium resolution ADCs.

An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range

This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]. Architectural choices such as the use of a residue amplifier are outlined that enable the high sample rate, low noise and power efficiency. The design is implemented on 0.18 μm CMOS with MIM capacitors and both 1.8 V and 5 V MOS devices. An LVDS interface is used to transfer the ADC result off chip.

An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz

This paper presents an 18-bit SAR ADC capable of −107dB THD for a 10V pk to pk 100kHz input. Distortion originating from the input switchs nonlinear on-resistance is cancelled by sampling the input onto two separate capacitor arrays, whose components are scaled to give the same nonlinear charge error, and then subtracting this charge during conversion. The new sampling scheme can support event-driven sampling, requires no active circuits and draws zero quiescent power.