Colin G. Lyden

An 18 b 12.5 MS/s ADC With 93 dB SNR

This paper presents a precision 18-bit 12.5 MS/s ADC that was designed primarily for digital X-ray imaging systems. This ADC was intended to have a faster output data rate than the precision successive approximation ADCs normally chosen for these systems but with similar DC accuracy and dynamic range. The chosen architecture consists of a pipeline of two multi-bit successive approximation converters. The first successive approximation ADC generates an initial coarse conversion result. The DACs within this converter are then used to generate a residue which is amplified by a residue amplifier before being converted by a second successive approximation ADC. Four comparators within each ADC allow 2 bits to be determined each bit trial. Capacitor mismatch errors are digitally corrected with error coefficients stored in non-volatile memory. Dither is used to reduce the effect of errors in the flash ADC within the second ADC. The ADC was implemented on 0.25 m CMOS process with PIP capacitors and achieves a SNR of 93 dB with a 50 kHz input tone. INL and DNL are within LSB and LSB respectively. Power consumption is 105 mW, excluding LVDS interface power.

An 18b 12.5MHz ADC with 93dB SNR

This ADC is aimed at medical imaging such as digital x-ray where multiple channels from a photodiode array are multiplexed to a number of ADCs. These ADCs need to have a dynamic range in excess of 90dB to cater for the distance and composition of tissues that the x-rays have passed through. INL matching between converters of about 1 LSB at the 16b level is also required to avoid visible artifacts across pixel boundaries. These INL and dynamic range specifications are met by a number of commercially available 16b successive approximation (SA) ADCs but none at conversion rates more than 4 MHz. Conversion rate can be increased by determining 2 or more bits per bit trial by using a low resolution flash within a SA ADC. In [1] the residue amplifier (RA) that drives the inputs of the flash converter is within the SA loop. Sufficient time must be allowed for this RA to settle to the required accuracy each bit trial. [2] has no gain between the SA DACs and the flash and so avoids any RA settling delays. However to avoid upsetting the SA algorithm, the flash comparator errors must remain smaller than the size of each trial space. As a result this latter approach has so far been limited to low to medium resolution ADCs.

An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range

This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]. Architectural choices such as the use of a residue amplifier are outlined that enable the high sample rate, low noise and power efficiency. The design is implemented on 0.18 μm CMOS with MIM capacitors and both 1.8 V and 5 V MOS devices. An LVDS interface is used to transfer the ADC result off chip.

A 0.18/spl mu/m 102dB-SNR mixed CT SC audio-band /spl Delta//spl Sigma/ ADC

A second-order mixed CT SC /spl Delta//spl Sigma/ modulator uses multi-bit feedback to reduce clock-jitter sensitivity. The chip is implemented in 0.18/spl mu/m CMOS using 3.3V I/O devices and achieves 102dB SNR in a 20kHz bandwidth by using chopper stabilization to reduce flicker noise. The ADC core draws 11.3mA from a 3.3V supply and occupies 0.65mm/sup 2/.

Sampling Circuits That Break the kT/C Thermal Noise Limit

Several circuit-level techniques are described which are used to reduce thermal noise and break the so-called kT/C limit. kT/C noise describes the total thermal noise power added to a signal when a sample is taken on a capacitor. In the first proposed technique, the sampled thermal noise is reduced by altering the relationship between the sampling bandwidth and the dominant noise source, providing a powerful, new degree of freedom in circuit design. In the second proposed technique, thermal noise sampled on an input capacitor is actively cancelled using an amplifier, so that the noise at the amplifier output can be controlled independently of input capacitor size. Measurements from two test chips are presented which demonstrate sampled thermal noise power reduction of up to 70% when compared to conventional kT/C-limited sampling.

Analysis of distributed resistance effects in MOS transistors

A method of modeling the distributed source and drain resistance effects in MOS transistors is discussed. Simulations performed using this technique are validated by comparisons with purpose-built structures. The method is then used to examine a problem which arises with the use of a high-temperature interconnect in three-dimensional silicon-on-insulator technologies. The results show how the resistivity of the interconnect affects the performance of the substrate devices of this technology, and the benefits achievable through further development of the existing interconnect technologies are outlined. Finally, the procedure is used to examine the effect of reduced contact size on standard MOS devices, and results wh1ich give general guidelines to the extent of the effect are presented. >

A 100dB SNR 2.5MS/s output data rate /spl Delta//spl Sigma/ ADC

A multi-bit cascaded 2-2-0 /spl Delta//spl Sigma/ modulator in 0.25/spl mu/m CMOS attains 100dB SNR in a 1MHz signal bandwidth. The complete A/D converter includes an on-chip operational amplifier for driving the large input capacitors dictated by kT/C noise, a reference buffer and a programmable decimation filter. The power consumption of the modulator including reference buffer is 475mW from a dual supply (2.5V and 5V).

Sampling circuits that break the kT/C thermal noise limit

Several circuit-level techniques are described which are used to reduce or cancel thermal noise and break the so-called kT/C limit. kT/C noise describes the total thermal noise power added to a signal when a sample is taken on a capacitor. In the first proposed technique, the sampled thermal noise is reduced by altering the relationship between the sampling bandwidth and the dominant noise source, providing a powerful, new degree of freedom in circuit design. In the second proposed technique, thermal noise sampled on an input capacitor is actively canceled using an amplifier, so that the noise at the amplifier output can be controlled independently of input capacitor size. Measurements from two test chips are presented which demonstrate sampled thermal noise power reduction of 48% and 67%, respectively, when compared with conventional kT/C-limited sampling.

Rapid IC performance yield and distribution prediction using a rotation of the circuit parameter principals components

Abstract Monte-Carlo techniques for prediction of IC yield in the presence of inter-die parameter variations are well established in the literature [Luigi P. Monte-Carlo simulation of semiconductor device and process modelling; critical review. IEEE Trans CAD 1990; CAD-9: 1164--76], but their use in commercial design is limited by their high computational cost. This paper presents a novel technique which shows a great reduction in the simulation cost and sustains the accuracy. It does this by first using Principal Component Analysis (PCA) [Cureton EE et al. Factor analysis: an applied approach. Hillsdale, New Jersey: Laurence Erlbaum Associates, 1983] to identify the significant orthogonal directions of variation in the process space. The next steps involve the development of an accurate approximation of the two dimensional yield boundary. Finally, an analytic integration in the process space provides the yield. The steps involved in the yield calculation also conveniently produce performance distributions and this is described.

5.7 A 19nV/√Hz-noise 2µV-offset 75µA low-drift capacitive-gain amplifier with switched-capacitor ADC driving capability

This paper describes a capacitive programmable-gain amplifier (CGA) with amplifier common-mode sampling (CMS) and switched-capacitor driving capability, compatible with many conventional switched-capacitor ADC inputs (SCAI) such as delta-sigma modulators or SAR ADCs. CGAs are popular for their low power, low noise and high precision [1,2]. The capacitive gain network is highly linear, does not dissipate static power and can be noiseless. Capacitors have excellent matching and temperature drift, which has a positive impact on offset/gain errors and their drift. They also offer a high input impedance at low frequencies and rail-to-rail operation, which makes them very suitable to interface with different types of sensors.