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Featured researches published by Derwin L. Jallice.


Archive | 1990

CMOS OFF CHIP DRIVER FOR FAULT TOLERANT COLD SPARING

Joseph Hoffman; Derwin L. Jallice; Yogishwar Puri; Randall G. Richards


Archive | 1999

Single event upset (SEU) hardened static random access memory cell

Ho Gia Phan; Derwin L. Jallice; Bin Li; Joseph Hoffman


Archive | 1990

Zero standby power, radiation hardened, memory redundancy circuit

Michael Kevin Ciraula; Christopher McCall Durham; Derwin L. Jallice


Archive | 1991

Glitch-proof powered-down on chip receiver with non-overlapping outputs

Michael Kevin Ciraula; Christopher M. Durham; Derwin L. Jallice


Archive | 1995

Extended segmented precharge architecture

Derwin L. Jallice; Christopher M. Durham; Michael Kevin Ciraula


Archive | 1993

Chipwahl Beschleunigungsschaltung für Speicher

Michael Kevin Ciraula; Christopher M. Durham; Derwin L. Jallice


Archive | 1991

CMOS off-chip-Treiber für eine fehlergeschützte kalte Ersatzschaltung CMOS off-chip driver for an error-protected cold equivalent circuit

Joseph Hoffman; Derwin L. Jallice; Yogishwar Puri; Randall G. Richards


Archive | 1990

Vorlade-Architektur von integrierten Speichern Precharge architecture of integrated memories

Michael Kevin Ciraula; Christopher McCall Durham; Reginald Eric Harrison; Derwin L. Jallice; Dave Christopher Lawson; Craig Lee Stephen


Archive | 1990

Precharge architecture of integrated memories

Michael Kevin Ciraula; Christopher McCall Durham; Reginald Eric Harrison; Derwin L. Jallice; Dave Christopher Lawson; Craig Lee Stephen


Archive | 1990

Null-Ruheleistung aufweisende, strahlungsfeste Speicherredundanzschaltung Zero-bias power having, radiation hardened memory redundancy circuit

Michael Kevin Ciraula; Christopher McCall Durham; Derwin L. Jallice

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