Christopher M. Durham

A 32nm 0.5V-supply dual-read 6T SRAM

Dual read port SRAMs play a critical role in high performance cache designs, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32nm metal-gate partially depleted (PD) SOI technology, for low-voltage applications. Hardware exhibits robust operation at 348MHz and 0.5V with a read and write power of 3.33 and 1.97mW, respectively, per 4.5KB active array with both read ports accessed at the highest activity data pattern. At a 0.6V supply, an access speed of 1.2GHz is observed.

Circuit Design Margin and Design Variability

In the preceding chapters, process variations and circuits styles were discussed. Each circuit style has its own reaction to variations of the process. Each variation must be accounted for to maintain the functionality and desired speed of the circuit across these distributions. All process parameter distributions are a function of the range that the parameter is critical both spatially and temporally. This chapter will investigate the variation of the process on static CMOS logic, dynamic domino, pass gate and DCVS logic.

Slack Borrowing and Time Stealing

With any circuit, clocking, and latching selection, the concept of how to fit more logic within a path between latches than is readily available always becomes an issue. That is, inevitably a logical pipeline partition will require more time than is available, for example, more than a full-cycle time in a master-slave system or a half-cycle in a two-phase separated-latch system. Depending on the circuit style, the latching structure, and the clocking strategy, obtaining this time can be classified as one of two categories, slack borrowing and time stealing (also commonly referred to as cycle stealing).

Non-Clocked Logic Styles

Non-clocked logic is ubiquitous in electronic design, due to a number of considerations including: Low power consumption Straightforward delay rule timing Inherent reliability and noise immunity Process variation and defect tolerance Migratability into successive technology generations. Deterministic diagnostic capability.

Clocked Logic Styles

In the preceeding chapter, nonclocked circuit topologies were shown generally to be versatile, reliable, and relatively low in power consumption. Clocked logic, on the other hand, is recognized for its performance advantages, which may be attributed to the following: 1. In Static CMOS, logic must be built redundantly; circuit operations must be realized in both NFET and PFET device structures to accomodate both up and down logic transitions. This reduces performance by adding gate fan-out load and interconnect RC. Higher device counts lead to longer interconnects, higher power consumption and bigger die1. 2. In static CMOS, even when the redundant structure is off, the added diffusion and overlap capacitive loads increase power and delay. 3. In Static CMOS, PFET devices must drive the same loads as NFET devices, at half the transconductance. This drives PFET devices to generally be 2X the width of NFET devices for balanced transitions. The impact is of particular concern structures such as PFET devices 5 and 6 in Figure 2.2a.