Diego P. Morales

Thermal drift reduction with multiple bias current for MOSFET dosimeters

New thermal compensation methods suitable for p-channel MOSFET (pMOS) dosimeters with the usual dose readout procedure based on a constant drain current are presented. Measuring the source-drain voltage shifts for two or three different drain currents and knowing the value of the zero-temperature coefficient drain current, I(ZTC), the thermal drift of source-drain or threshold voltages can be significantly reduced. Analytical expressions for the thermal compensation have been theoretically deduced on the basis of a linear dependence on temperature of the parameters involved. The proposed thermal modelling has been experimentally proven. These methods have been applied to a group of ten commercial pMOS transistors (3N163). The thermal coefficients of the source-drain voltage and the threshold voltage were reduced from -3.0 mV  °C(-1), in the worst case, down to -70 µV  °C(-1). This means a thermal drift of -2.4 mGy  °C(-1) for the dosimeter. When analysing the thermal drifts of all the studied transistors, in the temperature range from 19 to 36 °C, uncertainty was obtained in the threshold voltage due to a thermal drift of ±9 mGy (2 SD), a commonly acceptable value in most radiotherapy treatments. The procedures described herein provide thermal drift reduction comparable to that of other technological or numerical strategies, but can be used in a very simple and low-cost dosimetry sensor.

An application of reconfigurable technologies for non-invasive fetal heart rate extraction

This paper illustrates the use of a reconfigurable system for fetal electrocardiogram (FECG) estimation from mothers abdomen ECG measurements. The system is based on two different reconfigurable devices. Initially, a field-programmable analog array (FPAA) device implements the analog reconfigurable preprocessing for ECG signal acquisition. The signal processing chain continues onto a field-programmable gate array (FPGA) device, which contains all the communication and interfacing protocols along with specific digital signal processing blocks required for fundamental period extraction from FECG waveforms. The synergy between these devices provides the system the ability to change any necessary parameter during the acquisition process for enhancing the result. The use of a FPGA allows implementing different algorithms for FECG signal extraction, such as adaptive signal filtering. Preliminary works employ commercially available development platforms for test experiments, which suffice for the processing of real FECG signals from biomedical databases, as the presented results illustrate.

Noise Suppression in ECG Signals through Efficient One-Step Wavelet Processing Techniques

This paper illustrates the application of the discrete wavelet transform (DWT) for wandering and noise suppression in electrocardiographic (ECG) signals. A novel one-step implementation is presented, which allows improving the overall denoising process. In addition an exhaustive study is carried out, defining threshold limits and thresholding rules for optimal wavelet denoising using this presented technique. The system has been tested using synthetic ECG signals, which allow accurately measuring the effect of the proposed processing. Moreover, results from real abdominal ECG signals acquired from pregnant women are presented in order to validate the presented approach.

Merging FPGA and FPAA Reconfiguration Capabilities for IEEE 1451.4 Compliant Smart Sensor Applications

This work focuses on the application of both field programmable analog arrays (FPAAs) and field programmable gate arrays (FPGAs) as an unique system for implementing IEEE 1451.4 sensor interfaces. The inherent reconfigurability of these two hardware platforms allows increasing the versatility of the overall system, leading to a variety of sensor connectivity and remote measurement and control options.

Evaluation of a reconfigurable portable instrument for copper determination based on luminescent carbon dots

A portable reconfigurable platform for copper (Cu(II)) determination based on luminescent carbon dot (Cdots) quenching is described. The electronic setup consists of a light-emitting diode (LED) as the carbon dot optical exciter and a photodiode as a light-to-current converter integrated in the same instrument. Moreover, the overall analog conditioning is simply performed with one integrated solution, a field-programmable analog array (FPAA), which makes it possible to reconfigure the filter and gain stages in real time. This feature provides adaptability to use the platform as an analytical probe for carbon dots coming from different batches with some variations in luminescence characteristics. The calibration functions obtained that fit a modified Stern-Volmer equation were obtained using luminescence signals from Cdots quenching by Cu(II). The analytical applicability of the reconfigurable portable instrument for Cu(II) using Cdots has been successfully demonstrated in tap water analysis.

Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration

This work describes an analog reconfiguration technique for acquisition and processing of analog sensor signals that involves field programmable analog arrays (FPAAs) and field programmable gate arrays (FPGAs). The main objective is to exploit their natural reconfiguration capabilities that allow the increase of the analog-to-digital conversion (ADC) resolution and an adaptive post processing of the digital signal. This work is completed by the demonstration of this technique with an NTC temperature sensor signal, increasing the ADC resolution. The proposed system acquires the analog signal with filtering, amplifications and ADC being performed on the FPAA, while dynamically tuning the analog conditioning on the FPAA; after that, the FPGA processes the digital signal and delivers the final result to the end user, also involving the use of an embedded PicoBlaze.

Dynamical graph theory networks techniques for the analysis of sparse connectivity networks in dementia

Graph network models in dementia have become an important computational technique in neuroscience to study fundamental organizational principles of brain structure and function of neurodegenerative diseases such as dementia. The graph connectivity is reflected in the connectome, the complete set of structural and functional connections of the graph network, which is mostly based on simple Pearson correlation links. In contrast to simple Pearson correlation networks, the partial correlations (PC) only identify direct correlations while indirect associations are eliminated. In addition to this, the state-of-the-art techniques in brain research are based on static graph theory, which is unable to capture the dynamic behavior of the brain connectivity, as it alters with disease evolution. We propose a new research avenue in neuroimaging connectomics based on combining dynamic graph network theory and modeling strategies at different time scales. We present the theoretical framework for area aggregation and time-scale modeling in brain networks as they pertain to disease evolution in dementia. This novel paradigm is extremely powerful, since we can derive both static parameters pertaining to node and area parameters, as well as dynamic parameters, such as system’s eigenvalues. By implementing and analyzing dynamically both disease driven PC-networks and regular concentration networks, we reveal differences in the structure of these network that play an important role in the temporal evolution of this disease. The described research is key to advance biomedical research on novel disease prediction trajectories and dementia therapies.

Digital Signature Embedding Technique for IP Core Protection

The intellectual property protection of reusable design modules are becoming a problem with the expansion of this design strategy. This paper propose a new protection method for IP cores to be implemented over FPGAs. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The technique relies on a procedure that spreads a digital signature in cells of look-up tables of designs at HDL design level, not increasing the area of the system. The technique includes a procedure for signature extraction that allows to detect the ownership right without interfering the normal operation of the system and requiring minimal modifications to the system. The IPP technique has been implemented on programmable devices, with negligible performance penalties.

Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing

This work describes the application of both field programmable analog arrays (FPAAs) and field programmable gate arrays (FPGAs) for signal conditioning and processing in smart sensor applications. The main objective is to exploit their natural reconfiguration capabilities, which will expand the application field to more complex measurement and control systems. On the other hand, the introduction of IEEE 1451-compliant sensors allows for the development of multi-sensor and multi-purpose platforms, that may benefit from programmable technologies. Thus, this paper includes initial developments for IEEE 1451 smart sensor interfacing and its application to instrumentation.

Hardware implementation of a new ECC key distribution protocol for securing Wireless Sensor Networks

Security in Wireless Sensor Networks (WSNs) is a major challenge for extending its applications. In this paper, a new protocol for key distribution in WSNs is proposed. The method, based on Elliptic Curve Cryptography, and named ECGDH-1, performs a double round key distribution, sharing a group key among the different nodes. For accelerating the scalar-point operations to be performed in each node, a hardware coprocessor with low power consumption, and 8-bit interface for sensor motes is proposed. The cryptographic processor, named ECCB163sens_bus8 allows completing a scalar-point multiplication in 240us operating at 8MHz, while consuming only 0.028mJ by operation when implemented in a Spartan 6 device.