L. Parrilla

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores

In this paper, a procedure for intellectual property protection (IPP) of digital circuits called IPP@HDL is presented. Its aim is to protect the author rights in the development and distribution of reusable modules by means of an electronic signature. The technique relies on hosting the bits of the digital signature within memory structures or combinational logic that are part of the system, at the high level description of the design. Thus, the area of the system is not increased and the signature is difficult to change or to remove without damaging the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system and without interfering its normal operation. The benefits of the presented procedure are illustrated with programmable logic and cell-based application-specific integrated circuit examples with several signature lengths. These design examples show no performance degradation and a negligible area increase, while probabilistic analyses show that the proposed IPP scheme offers high resistance against attacks.

Ring oscillators as thermal sensors in FPGAs: Experiments in low voltage

In this paper, some experiments about thermal sensors based on ring-oscillator in low-voltage Virtex series FPGAs are presented. A non linear effect in the frequency-temperature response has been detected, and the sensibility of frequency with respect to voltage variations is greater than the measured in previous works. A quadratic polynomial function fits better the sensor response, and an increment in the number of inverters in the oscillator is effective to reduce the voltage sensibility.

A RNS-based matrix-vector-multiply FCT architecture for DCT computation

A Field-Programmable Logic (FPL) implementation of the Discrete Cosine Transform (DCT) based on the Residue Number System (RNS) is presented. It uses a combination of the Fast Cosine Transform (FCT) algorithm and the matrix-vector multiplication (MVM). This paper shows that the RNS-based FCT-MVM implementation provides a throughput improvement over the equivalent binary system up to 72%, while its advantage over the binary distributed arithmetic implementation is up to 128%.

A new architecture to compute the discrete cosine transform using the quadratic residue number system

A new methodology to compute the N-point DCT (Discrete Cosine Transform) in the QRNS (Quadratic Residue Number System) is presented, with a significant improvement in complexity and speed compared to the corresponding binary version. This reduction in the total number of arithmetic adders and multipliers is up to 21% and 26% for an 8-point and a 16-point DCT, respectively. In addition, large and slow binary adders and multipliers with a long carry propagation delay are replaced by high-speed small word-length modular adders and LUT (Look-Up Table) multipliers. When a Field Programmable Logic (FPL) implementation using Altera FLEX10KE devices of the proposed architecture for the 8-point DCT is considered, throughput is three times better than that obtained with the corresponding fixed point 2s complement binary implementation.

An application of reconfigurable technologies for non-invasive fetal heart rate extraction

This paper illustrates the use of a reconfigurable system for fetal electrocardiogram (FECG) estimation from mothers abdomen ECG measurements. The system is based on two different reconfigurable devices. Initially, a field-programmable analog array (FPAA) device implements the analog reconfigurable preprocessing for ECG signal acquisition. The signal processing chain continues onto a field-programmable gate array (FPGA) device, which contains all the communication and interfacing protocols along with specific digital signal processing blocks required for fundamental period extraction from FECG waveforms. The synergy between these devices provides the system the ability to change any necessary parameter during the acquisition process for enhancing the result. The use of a FPGA allows implementing different algorithms for FECG signal extraction, such as adaptive signal filtering. Preliminary works employ commercially available development platforms for test experiments, which suffice for the processing of real FECG signals from biomedical databases, as the presented results illustrate.

Noise Suppression in ECG Signals through Efficient One-Step Wavelet Processing Techniques

This paper illustrates the application of the discrete wavelet transform (DWT) for wandering and noise suppression in electrocardiographic (ECG) signals. A novel one-step implementation is presented, which allows improving the overall denoising process. In addition an exhaustive study is carried out, defining threshold limits and thresholding rules for optimal wavelet denoising using this presented technique. The system has been tested using synthetic ECG signals, which allow accurately measuring the effect of the proposed processing. Moreover, results from real abdominal ECG signals acquired from pregnant women are presented in order to validate the presented approach.

Automated Signature Insertion in Combinational Logic Patterns for HDL IP Core Protection

This paper presents significant improvements to previous watermarking technique for intellectual property protection (IPP) of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using resources included within the original system. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system. The new advances refer to increasing the applicability of this watermarking technique to any design and the provision of an automatic tool for signature hosting that, in addition to easy the signature hosting, leads to reduced area penalties. Synthesis results show that the application of the proposed watermarking strategy results in negligible degradation of system performance and very low area penalties.

Intellectual Property Protection for RNS Circuits on FPGAs

A new procedure for Intellectual Property Protection (IPP) of circuits based on the residue number system (RNS) and implemented over FPL devices is presented. The aim is to protect the author rights in the development and distribution of reusable modules (IP cores) by means of an electronic signature embedded within the design. The presented protection scheme is oriented to circuits based on the RNS but can be easily extended to systems implemented on programmable devices. As an example, a 128-bit signature is introduced into a CIC filter without affecting performance and negligible area increase.

A new implementation of the discrete cosine transform in the residue number system

A field-programmable logic (FPL) implementation of a discrete cosine transform (DCT) based on the residue number system (RNS) is presented. Compared with a binary distributed arithmetic implementation, the presented architecture provides approximately 21% throughput improvement. Moreover, the performance improvement over a conventional binary implementation is up to 103%. This is achieved due to the synergy between RNS and modern FPL device families.

Intellectual property protection of IP cores through high-level watermarking

In this paper a watermarking technique for Intellectual Property Protection (IPP) of FPGA-based systems is proposed. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The proposed watermarking technique relies on a procedure that spreads the digital signature in cells of memory structures at Hardware Description Language (HDL) design level, not increasing the area of the system. This signature is preserved through synthesis, placement and routing processes. The technique includes a procedure for signature extraction requiring minimal modifications to the system. Thus, it is possible to detect the ownership rights without interfering the normal operation of the system and providing high invulnerability. To illustrate the properties of the proposed watermarking technique, both protected and unprotected design examples are compared in terms of area and performance. The analysis of the results shows that the area increase is very low while throughput penalization is almost negligible.