Dietmar Petras

parSC: synchronous parallel systemc simulation on multi-core host architectures

Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and verification. Its practicability is put at risk by the growing MPSoC complexity. This work presents a conservative synchronous parallel simulation approach along with a SystemC framework to accelerate tightly-coupled MPSoC simulations on multi-core hosts. Key contribution is the implementation strategy, which utilizes techniques from the high-performance computing domain. Results show speed-ups of up to 4.4 on four host cores.

legaSCi: Legacy SystemC Model Integration into Parallel Systemc Simulators

Virtual prototyping of parallel and embedded systems increases insight into existing computer systems. It further allows to explore properties of new systems already during their specification phase. Virtual prototypes of such systems benefit from parallel simulation techniques due to the increased simulation speed. One common problem full system simulator implementers face is the revision and integration of legacy models coded without thread-safety and deterministic behavior in mind. To lessen this burden, this paper presents a methodology to integrate unmodified SystemC legacy models into parallel SystemC simulators. Using the proposed technique, the embedded platform simulator of the EU FP7 project EURETILE, which inherited a number of legacy models from its predecessor project SHAPES, has been transformed into a parallel simulation platform, demonstrating speed-ups of up to 3.36 on four simulation host cores.

A checkpoint/restore framework for systemc-based virtual platforms

The ability to restore a Virtual Platform from a previously saved simulation state can considerably shorten the typical edit-compile-debug cycle for software developers and therefore enhance productivity. This paper presents a Checkpoint/Restore solution specifically tailored towards the needs of SystemC-based Virtual Platforms. Apart from restoring the simulation process from a checkpoint image, it also takes care of re-attaching debuggers and interactive GUIs to the restored Virtual Platform. The checkpointing is handled automatically for most of the SystemC modules, only the usage of host OS resources requires user provision. Two concrete code examples demonstrate that the required changes to an existing Virtual Platform are a simple developer task consisting of minor source code modifications. A case study based on the SHAPES Virtual Platform is conducted to investigate the applicability of the proposed framework in a realistic system environment.

SystemC-link: Parallel SystemC simulation using time-decoupled segments

Virtual platforms have become essential tools in the design process of modern embedded systems. Their accessibility and early availability make them ideal tools for design space exploration and debugging of target specific software. However, due to increasing platform complexity and the need to simulate more and more processors simultaneously, performance of virtual platforms degrades rapidly. This work presents SystemC-Link, a segment based parallel simulation framework for SystemC simulators. It achieves high simulation performance by using a parallel and time-decoupled simulation approach. Furthermore, it offers a virtual sequential environment for each simulation segment. This enables use of legacy models by allowing operation on global state without risking race conditions during parallel simulation. The approach is evaluated in a variety of scenarios, including a contemporary multi-core platform based on the OpenRISC architecture running Linux. For this benchmark, a 3.2× higher simulation performance was achieved with SystemC-Link compared to standard SystemC on a regular workstation PC.

Checkpointing SystemC-Based Virtual Platforms

The ability to restore a virtual platform from a previously saved simulation state can considerably shorten the typical edit-compile-debug cycle for software developers and therefore enhance productivity. For SystemC based virtual platforms VP, dedicated checkpoint/restore C/R solutions are required, taking into account the specific characteristics of such platforms. Apart from restoring the simulation process from a checkpoint image, the proposed checkpoint solution also takes care of re-attaching debuggers and interactive GUIs to the restored virtual platform. The checkpointing is handled automatically for most of the SystemC modules, only the usage of host OS resources requires user provision. A process checkpointing based C/R has been selected in order to minimize the adaption required for existing VPs at the expense of large checkpoint sizes. This drawback is overcome by introducing an online compression to the checkpoint process. A case study based on the SHAPES Virtual Platform is conducted to investigate the applicability of the proposed framework as well as the impact of checkpoint compression in a realistic system environment.