Jan Henrik Weinstock

HySim: a fast simulation framework for embedded software development

Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology, it still suffers from low simulation speed compared to real hardware. Especially for embedded software developers simulation speed close to real time is important in order to efficiently develop complex software. In this paper a novel, retargetable, hybrid simulation framework (HySim) is presented which allows switching between native code execution and ISS-based simulation. To reach a certain state of an application as fast as possible, all platform-independent parts of the application are directly executed on the host, while the platform dependent code executes on the ISS. During the native code execution a performance estimation is conducted. A case study shows that speed-ups ranging from 7× to 72× can be achieved without compromising debugging accuracy. The performance estimation during native code execution shows an average error of 9.5%.

Time-decoupled parallel SystemC simulation

With increasing system size and complexity, designers of embedded systems face the challenge of efficiently simulating these systems in order to enable target specific software development and design space exploration as early as possible. Todays multicore workstations offer enormous computational power, but traditional simulation engines like the OSCI SystemC kernel only operate on a single thread, thereby leaving a lot of computational potential unused. Most modern embedded system designs include multiple processors. This work proposes SCope, a SystemC kernel that aims at exploiting the inherent parallelism of such systems by simulating the processors on different threads. A lookahead mechanism is employed to reduce the required synchronization between the simulation threads, thereby further increasing simulation speed. The virtual prototype of the European FP7 project EURETILE system simulator is used as demonstrator for the proposed work, showing a speedup of 4.01× on a four core host system compared to sequential simulation.

legaSCi: Legacy SystemC Model Integration into Parallel Systemc Simulators

Virtual prototyping of parallel and embedded systems increases insight into existing computer systems. It further allows to explore properties of new systems already during their specification phase. Virtual prototypes of such systems benefit from parallel simulation techniques due to the increased simulation speed. One common problem full system simulator implementers face is the revision and integration of legacy models coded without thread-safety and deterministic behavior in mind. To lessen this burden, this paper presents a methodology to integrate unmodified SystemC legacy models into parallel SystemC simulators. Using the proposed technique, the embedded platform simulator of the EU FP7 project EURETILE, which inherited a number of legacy models from its predecessor project SHAPES, has been transformed into a parallel simulation platform, demonstrating speed-ups of up to 3.36 on four simulation host cores.

Dynamic many-process applications on many-tile embedded systems and HPC clusters

In the next decade, a growing number of scientific and industrial applications will require power-efficient systems providing unprecedented computation, memory, and communication resources. A promising paradigm foresees the use of heterogeneous many-tile architectures. The resulting computing systems are complex: they must be protected against several sources of faults and critical events, and application programmers must be provided with programming paradigms, software environments and debugging tools adequate to manage such complexity. The EURETILE (European Reference Tiled Architecture Experiment) consortium conceived, designed, and implemented: 1- an innovative many-tile, many-process dynamic fault-tolerant programming paradigm and software environment, grounded onto a lightweight operating system generated by an automated software synthesis mechanism that takes into account the architecture and application specificities; 2- a many-tile heterogeneous hardware system, equipped with a high-bandwidth, low-latency, point-to-point 3D-toroidal interconnect. The inter-tile interconnect processor is equipped with an experimental mechanism for systemic fault-awareness; 3- a full-system simulation environment, supported by innovative parallel technologies and equipped with debugging facilities. We also designed and coded a set of application benchmarks representative of requirements of future HPC and Embedded Systems, including: 4- a set of dynamic multimedia applications and 5- a large scale simulator of neural activity and synaptic plasticity. The application benchmarks, compiled through the EURETILE software tool-chain, have been efficiently executed on both the many-tile hardware platform and on the software simulator, up to a complexity of a few hundreds of software processes and hardware cores.

Scandal: Systemc analysis for nondeterminism anomalies

SystemC is the de facto standard language for electronic system level design and simulation. SystemC simulations may contain nondeterminism caused by dependencies on the process execution order (PEO) due to data dependencies of SystemC logical processes (LP) within delta-cycles. In practice, often this is not an issue, since simulation execution appears to be deterministic due to deterministic SystemC scheduler implementations. However, to satisfy the increasing need for simulation speed, parallel SystemC engines are being researched: With no fixed strict total order among LPs executed in parallel, nondeterministic behavior is more likely to surface and more difficult to debug, threatening the viability to use simulation especially for debugging use-cases. This work presents a new method to test for nondeterminism: Anomalies are detected by running a simulation twice in sequential simulation mode while systematically varying the PEO, and without the need for source code analysis. Feasibility is demonstrated with several case studies.

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems

EURETILE investigates foundational innovations in the design of massively parallel tiled computing systems by introducing a novel parallel programming paradigm and a multi-tile hardware architecture. Each tile includes multiple general-purpose processors, specialized accelerators, and a fault-tolerant distributed network processor, which connects the tile to the inter-tile communication network. This paper focuses on the EURETILE software design flow, which provides a novel programming environment to map multiple dynamic applications onto a many-tile architecture. The elaborated high-level programming model specifies each application as a network of autonomous processes, enabling the automatic generation and optimization of the architecture-specific implementation. Behavioral and architectural dynamism is handled by a hierarchically organized runtime-manager running on top of a lightweight operating system. To evaluate, debug, and profile the generated binaries, a scalable many-tile simulator has been developed. High system dependability is achieved by combining hardware-based fault awareness strategies with software-based fault reactivity strategies. We demonstrate the capability of the design flow to exploit the parallelism of many-tile architectures with various embedded and high performance computing benchmarks targeting the virtual EURETILE platform with up to 192 tiles.

SystemC-link: Parallel SystemC simulation using time-decoupled segments

Virtual platforms have become essential tools in the design process of modern embedded systems. Their accessibility and early availability make them ideal tools for design space exploration and debugging of target specific software. However, due to increasing platform complexity and the need to simulate more and more processors simultaneously, performance of virtual platforms degrades rapidly. This work presents SystemC-Link, a segment based parallel simulation framework for SystemC simulators. It achieves high simulation performance by using a parallel and time-decoupled simulation approach. Furthermore, it offers a virtual sequential environment for each simulation segment. This enables use of legacy models by allowing operation on global state without risking race conditions during parallel simulation. The approach is evaluated in a variety of scenarios, including a contemporary multi-core platform based on the OpenRISC architecture running Linux. For this benchmark, a 3.2× higher simulation performance was achieved with SystemC-Link compared to standard SystemC on a regular workstation PC.

Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators

Simulators are used to aid the design of computer systems. Together with the computational power of computer systems, the demands towards their simulators are growing regarding speed, flexibility, as well as the predictability of their behavior. To increase simulation speed, simulation models are abstracted and simulated in parallel. To reduce simulator development time and to provide the greatest possible modeling flexibility, SystemC allows models to be written using C++ without restrictions. All three means, especially when used in combination, also increase the difficulty to reason about the behavior of the resulting simulator, in the worst case leading to unpredictable simulation behavior. This may threaten the fitness of simulators for demanding use-cases like the debugging of race conditions. This work discusses likely causes and impact of nondeterministic simulator behavior. Three examples taken from real-life models are used to illustrate the matter.

Parallel SystemC simulation for ESL design using flexible time decoupling

Engineers of next generation embedded systems heavily rely on virtual platforms as central tools in their design process. Yet, the ever increasing HW/SW complexity degrades the simulation performance of those platforms and threatens their viability as design tools. With multi-core workstations today being widely available, the transition towards parallel simulation technologies seems obvious. Recently published parallel SystemC simulators use time-decoupling to achieve high simulation performance on modern SMP machines. However, those simulators have to identify all cross-thread communication ahead of time. This work presents an approach how to overcome this limitation and to enable time-decoupled simulation for mainstream SystemC simulators, achieving a speedup of up to 3.4× on a quad-core host.

Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting

The ever-growing need for energy efficient computation requires adequate support for energy-aware thread scheduling that offers insight into a systems behavior for improved application energy/performance optimizations. Runtime accurate monitoring of energy consumed by every component of a multi-core embedded system is an important feature to be considered for future designs. Although, important steps have been made in this direction, the problem of distributing energy consumption among threads executed on different cores for shared components remains an ongoing struggle. We aim at designing a generic low-cost and energy efficient hardware infrastructure which supports thread level energy accounting of hardware components in a multi-core system. The proposed infrastructure provides upper software layers with per thread and per component energy accounting API, similar with performance profiling functions. Implementation results indicate that the proposed solution adds around 10i¾ź% resource overhead to the monitored system. Regarding the power estimates, the one derived by our solution achieves a correlation degree of more than 95i¾ź% with the ones obtained from physical power measurements.