Dietmar Schmunkamp

S/390 parallel enterprise server generation 3: a balanced system and cache structure

Since initiating the information technology industry-wide transition from bipolar to CMOS technology with the first generation of S/390® processors in 1994, IBM reached another major milestone with the introduction of the third generation in September 1996. The balanced system and cache structure and the modularity of the components of Generation 3 support a wide performance range from a uniprocessor to a high-performance multiprocessing system. Because of this modularity, Generation 4 is also based on this structure.

Run-control migration from single book to multibooks

This paper describes the migration of the hardware-implemented run-control functions from a single-book structure with one flexible service processor (FSP) and one service element (SE) per system to a multibook structure with one FSP per book and one SE per system. The new system structure required two new interfaces between the clock chips on the different books. The first interface is required for dynamic configuration data exchange between books. The alternative path via the SE would not meet the performance requirements. This interface is available in the initial millicode load flow before the L2 caches with their ring structure are operational. Another requirement is the necessity of starting and stopping all books synchronously. The second additional interface between the clock chips on different books enables this function. Nevertheless, the hardware implementation is so flexible that each book may operate independently of the other books. The clock chips are connected as a peer-to-peer network, so no special master is necessary in the system.

The clock, test and maintenance control chip of the IBM ES/9221

Abstract The design of the Clock, Test and Maintenance (CTM) control chip for an IBM ES/9221 microprocessor is presented in this paper. This CTM chip provides all functions to run built-in random pattern selftest and a Boundary Scan Chip Interconnection test besides supporting the normal mode of functional operation. In addition it allows to initialize and monitor all system latches during functional and test mode. All chips of the system are accessed from the CTM chip via a Test Access Bus (TAB).