Klaus J. Getzlaff

S/390 parallel enterprise server generation 3: a balanced system and cache structure

Since initiating the information technology industry-wide transition from bipolar to CMOS technology with the first generation of S/390® processors in 1994, IBM reached another major milestone with the introduction of the third generation in September 1996. The balanced system and cache structure and the modularity of the components of Generation 3 support a wide performance range from a uniprocessor to a high-performance multiprocessing system. Because of this modularity, Generation 4 is also based on this structure.

A CMOS mainframe processor with 0.5- mu m channel length

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 mu m. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0- mu m technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability. >

A mainframe processor in CMOS technology with 0.5 mu m channel length

A prototype of a processor chip set with a mainframe architecture is implemented using five CMOS standard cell chips. High performance is achieved by wide buses and a RISC- (reduced-instruction-set-computer) like implementation of frequently used instructions. The chip set consists of four units: (1) an instruction processor chip which fetches and decodes the instructions and contains the microcode storage; (2) cache chips which contain the address translation for up to 19 virtual address spaces, a four-way set-associative 16-kByte data/instruction cache, and a 32-B instruction buffer, which is loaded 16 B/cycle from the cache; (3) a fixed-point processor chip which contains the fixed-point registers and arithmetic and a second adder for the address calculation (base+displacement+index); (4) a floating-point processor chip which contains the floating-point registers, multiplier, and arithmetic unit. The processor is based on a four-stage pipeline (five stages for floating-point instructions).<<ETX>>

A 60 × 58 Integrated Multiplier

A dense 60 × 58 Multiplier will be described which is integrated on a chip containing a complete Coprocessor. The Multiplier has been fabricated in a triple-metal, single-polysilicon CMOS process with 1.0 um lithography and CMOS devices with 0.5 um effective channel length. Circuit techniques are described that obtain a multiplier with high density (3.5mm × 5.7mm) and high speed. The typical delay is 18 ns.