Dietrich Boettle

Design and implementation of a diffserv enabled HFC system offering Strict QoS support

Widespread deployment of Hybrid Fiber Coaxial (HFC) systems created a new residential access platform upgrading traditional cable TV networks, which were limited to distributed services. This evolution is driven by demand for faster Internet access from customers frustrated by slow telephone line and ISDN modem speeds. As residential traffic with voice and video-intensive content proliferates, the current generation of cable modems, which are oriented towards best-effort traffic, will need to be enhanced with new capabilities to handle the increased bandwidth and quality requirements. To integrate telecom services presenting diverse quality requirements over the same HFC access infrastructure necessitates a degree of isolation of traffic classes. The difficulty of handling finer aggregations because of the limited MAC reservation resources and the cost limitation of residential access make the scalability of the differentiated services architecture as relevant in the HFC access network as in any traffic multiplexer. An implementation integrating IP and ATM and aligning the system to the DiffServ philosophy is presented in this paper. It constitutes an affordable system solution for residential customers enabling the support of QoS-demanding services.

Realization of an ATM-based HFC demonstrator with high upstream capacity

Within the framework of the ACTS project ATHOC (ATM applications on Hybrid Optical fiber Coax), cable TV modems and hybrid fibre coax (HFC) systems have been realized, demonstrating the basic technologies which are common to the different HFC standardisation work-groups. The ATHOC prototypes employ 64-QAM modulation for the downstream and burst mode QPSK modulation for the upstream transmission, respectively, in order to achieve 40 Mb/s and 3 Mb/s. Time division multiple access (TDMA) is the method which is implemented to give all users access to the shared medium of the tree-and-branch CATV network. The article clarifies the HFC system concept which was implemented. The functions of the access network adaptation in the headend and the access network termination at the users premises are described.

A 16 x 16 switch element for 1.2 gbit/s in 0.8 μm bicmos technology

The paper describes a monolithic integrated matrix chip with 16 inputs and 16 outputs. Time division signals with bit rates of up to 1.24 Gbit/s can be applied to each of these inputs and outputs. The time division signals comprise 8 channels of 155 Mbitls and the channels are nested bit by bit. The 1.24 Gbit/s input signals are regenerated by amplitude and in phase and are placed in parallel. Within the chip, the signal can be switched channel by channel at the 155 Mbitls level. The signals are then serialized to 1.24 Gbit/s. To aid implementation, bipolar technology is incorporated in the high speed part and cmos technology is incorporated in the 155 Mbitls part. The functions of the chip are described and some applications, such as its use in an atm switch network, will be mentioned. First samples of the chip are already available. The descriptions refer to simulation results and measurements taken from first samples.Résuméľ article décrit un circuit intégré monolithique à 16 entrées et 16 sorties, pouvant commuter des signaux multiplexés dans le temps à des débits binaires jusqu’ à 1,24 Gbit/s. Ces signaux combinent 8 signaux à 155 Mbitls avec imbrication bit par bit. Les signaux ď entrée sont régénérés en amplitude et en phase, puis mis en parallèle. La commutation a lieu au niveau 155 Mbit/s, puis les signaux sont mis en série. La partie à haut débit utilise des circuits à technologie bipolaire et la partie à bas débit des circuits à technologie mos complémentaire (cmos). Des résultats de mesure sont présentés, ainsi que des applications, retournent dans un réseau de connexion atm.