Dietrich Stephani

Anisotropy of the electron Hall mobility in 4H, 6H, and 15R silicon carbide

Hall effect measurements in a Hall‐bar configuration are performed on nitrogen‐doped n‐type bulk 4H, 6H, and 15R SiC single crystals cut into small parallelepipeds with their longest edges either parallel or perpendicular to the c axis. In the temperature range investigated (40–700 K), an anisotropy of the electron Hall mobility is observed in all three polytypes. While the mobility perpendicular to the c axis—with magnetic field perpendicular or parallel to the c axis—is greater than the mobility parallel to the c axis for 6H and 15R SiC, 4H SiC shows the opposite behavior.

Enhanced channel mobility of 4H–SiC metal–oxide–semiconductor transistors fabricated with standard polycrystalline silicon technology and gate-oxide nitridation

This work presents improved channel mobility of n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on 4H–SiC, achieved by gate-oxide nitridation in nitric oxide. Lateral enhancement mode MOSFETs were fabricated using standard polycrystalline silicon gate process and 900 °C annealing for the source and drain contacts. The low field mobility of these MOSFETs was as high as 48 cm2/Vs together with a threshold voltage of 0.6 V, while the interface state density—determined from the subthreshold slope—was about 3×1011 eV−1 cm−2. The 43-nm-thick gate oxide of coprocessed metal–oxide–semiconductor structures exhibited a breakdown field strength of 9 MV/cm.

SiC power devices with low on-resistance for fast switching applications

Silicon carbide switching devices exhibit superior properties compared to silicon devices. Low specific on-resistance for high breakdown voltages is believed to be the most outstanding feature of SiC power switching devices. In this paper, MOSFETs and JFETs capable to block 1800 V with a specific on-resistance of 47 m/spl Omega/ cm/sup 2/ and 14.5 m/spl Omega/ cm/sup 2/, resp., are discussed. However, there are additional advantages making SiC devices attractive for the system designer. The authors present fast recovery of the 6H-SiC MOSFET reverse diode (Q/sub rr/ 30 nC, t/sub rr/ 20 ns) and fast switching as well as short circuit capability (1 ms) of vertical VJFETs. Finally, a short outlook to future SiC switching devices is given.

4H-SiC Power MOSFET Blocking 1200V with a Gate Technology Compatible with Industrial Applications

A normally off 4H-SiC power MOSFET blocking 1200 V is presented. Its structure, process and electrode materials are designed as close as possible to that of standard Si power MOSFETs, especially the gate electrode is made of pol ycrystalline silicon. The gate oxide is prepared by oxidation in nitrous oxide. In order to make the device compatible with standard gate drivers for power electronics the gate oxide thicknes s has been increased to 72 nm. With respect to long term stability the device is character ized at a maximum oxide field strength of 2.5 MV/cm. Onand off-state characteristics are presented and analy zed in detail. Introduction Improvements of the inversion layer mobility of 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) were reported recently by using gate oxide nitridation [1-4]. Values up to 48 cm/Vs resulted for lateral 4H-MOSFETs prepared on low doped p-type epilayers. This is remarkable since with thermal oxidation by oxy gen values below 1 cm /Vs were typical. For vertical MOSFETs 4H-SiC was seen as the worst choice from inversion channel mobility point of view, in spite of its high bulk mobility. As point ed out in [5], the inversion channel mobility strongly depends on the polytype. This effect i s most likely caused by carbon related surface states energetically fixed to around 2.9 eV above the valence band. Depending on the band gap of the polytype they act as near interface t raps, more or less overlapping with the conduction band edge. Consequently a higher channel mobility can be achieved using 15Rand 6H-SiC polytypes. But on the other hand the bulk mobilit y f 6HSiC parallel to the c-axis is much lower and makes 6H-SiC les s suitable for power devices. 15R-SiC would be the best choice but is not commercially available. This paper combines the method of forming a gate oxide by nitridation [ 1] with the technology developed for vertical SiC power MOSFETs described in [6]. In this case a polycrystalline silicon gate was used which is standard for sili con power MOSFET technology. Furthermore, the gate oxide thickness was significantly increased in order to meet the requirements of industrial power applications: compatibility wit h standard gate driving circuitry (gate source voltages within ±20 V) and long term stability obtained by strictly limiting the oxide field strength to 2.5 MV/cm. Device and Fabrication A cell structure of the so called triple implanted vertical MO SFET is sketched in Fig. 1. One can easily imagine that structure, process and electr od materials are designed as close as possible to the well known silicon DMOS. The device is planar and thus favora ble f fabrication. Characteristic design data are listed in Table 1. I n particular, if the inversion layer dominates the on-resistance it is important to achieve a gate le ngth as homogeneous as possible. For this purpose a self aligning process has been developed. The p-type body diode as well as the n-type source implantation of the MOSFET cell a re defined by only one mask. Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 769-772 doi:10.4028/www.scientific.net/MSF.433-436.769

First results on silicon carbide vapour phase epitaxy growth in a new type of vertical low pressure chemical vapour deposition reactor

In this paper a new concept for silicon carbide vapour phase epitaxy (VPE) will be presented. It is based on the rotating disk technology well known in the field of III–V epitaxy. First results will be given showing excellent structural quality of the epitaxial layers together with high growth rates up to 5 μm/h and good uniformity of layer thickness over 1 inch wafers. The CSi-ratio in the process can be varied over a wide range (0.35-2.3 at 3 μm/h) without loss of surface quality. This enables a precise control of the site competition effect and, therefore, of the incorporation of acceptor and donor impurities. Thus, non-intentionally doped p- (CSi > 1) and n-type (CSi < 0.7) epilayers with carrier concentrations considerably below 1016 cm−3 can be grown.

Dynamic characteristics of high voltage 4H-SiC vertical JFETs

We have developed a novel structure for a fully implanted, normally-on vertical junction field effect transistor (VJFET) and fabricated prototypes with blocking voltages between 600 and 1000 V. Mounting the SiC VJFET together with a 50 V Si MOSFET on a DCB substrate in a cascode circuit, we obtain a normally-off high voltage switch. The specific on-resistance of the VJFET was sufficiently low, in the range of 18 to 40 m/spl Omega/cm/sup 2/, for various blocking voltages. The dynamic behaviour shows turn-off times between 50 ns and 2 /spl mu/s due to the RC-product of two different p-gate networks.

SILICON CARBIDE JUNCTION FIELD EFFECT TRANSISTORS

The chapter will give an overview about the theory of JFETs with special attention to the wide band gap issues related to SiC. After a comprehensive discussion of relevant structures and topologies experimental results are presented and discussed. Especially vertical structures are in the focus of this chapter. Characteristic I-V data will be shown as well as application specific solutions regarding the temperature behavior or the ruggedness of the devices. The status of the JFETs technology will be judged and compared to alternative solutions like MOSFEts or lateral JFETs. Finally, an outlook will be given regarding targeted applications for SiC VJFETs and the resulting requirements as targets for future improvements.

Stacked high voltage switch based on SiC VJFETs

Based on the serial connection of high voltage SiC VJFETs a stacked solution able to block very high voltages is presented. By connecting VJFETs in series, a unipolar high voltage switch with 8kV blocking voltage and an on-resistance of 2/spl Omega/ was fabricated. The basic functions of this stacked switch are analyzed by discussing the electrical behavior. The static and dynamic behavior indicates an interesting perspective for high voltage and high power applications. Especially the dynamics are carefully analyzed using a low voltage version of the stacked solution. Additionally, the potential of SiC VJFETs as a 4kV single switch is demonstrated.

Properties and Suitability of 4H-SiC Epitaxial Layers Grown at Different CVD Systems for High Voltage Applications

This work reports on properties of epitaxial grown SiC layers and their suitability for high voltage devices using cold wall and hot wall CVD systems. Differences of fundamental machine parameters like temperature gradients and flow conditions were investigated. Based on these parameters structural and electrical layer properties were analyzed and compared. The layer suitability for high voltage devices was proven using pin-diodes with Al-implanted emitters.

Switching behaviour of fast high voltage SiC pn-diodes

4H-SiC p-n diodes with an active area of 1 mm/sup 2/ and up to 3 kV blocking voltage have been fabricated, characterized and compared to simulations. The static forward characteristics demonstrate the expected forward power loss with a negative temperature coefficient. The diodes exhibit a stable avalanche breakdown, showing a small positive temperature coefficient (0.3 V/K). The turn-on switching behaviour shows a relatively small voltage overshoot as compared to silicon diodes. The turn-off resembles that of a Schottky diode. In both cases, the dynamics can be attributed to a rapid recombination of the storage charge, even under high forward injection conditions. Numerical simulations may point to a local lifetime reduction at the p-n junction.