Dilip K. Bhavsar

An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264

An innovative self-test and self-repair technique supports built-in self-test and built-in self-repair of large embedded RAM arrays with spare rows and columns. The technique generates and analyzes the required failure bitmap information on the fly during self-test and then automatically repairs and verifies the repaired RAM arrays.

An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes

Tbts paper presents an arclcecrute for niakms the EEE Standard 1139.1 lest acces port did dl it? major provisions available on a system b~ckplaae It proposes a powerful. low-cost alternabve for system-wide comnim~ication for test and mamtenance purposes. using one chip-to-system test access protocol The bus interconnectton method employed in the xchtecture inherently accommcdates enipty slots in arbitrary posinom in the system back-plane without Qsrupnng the test bus connecavity or the test conimumcatlons

Testability strategy of the Alpha AXP 21164 microprocessor

This paper describes the testability strategy and design-for-test features of the Alpha AXP 21164 microprocessor. It discusses the specific testability and manufacturability issues of the chip and the innovative solutions employed to solve them.

Alpha 21164 testability strategy

A custom DFT strategy solved specific testability and manufacturing issues for this high performance microprocessor. Hardware and software assisted self test and self repair features helped meet aggressive schedule and manufacturing quality and cost goals.

Testability access of the high speed test features in the Alpha 21264 microprocessor

A novel on-chip testability access architecture provides comprehensive tester-driven access to the Alpha 21264 microprocessors testability features during manufacturing. It also allows simple automatic chip-initiated access that leverages the same features during normal chip operation. The architecture uses the IEEE Std 1149.1 to access all test features by creatively solving a number of problems in accessing the chips at-speed testability features from an asynchronous test port and slow tester.

Automatic generation of critical-path tests for a partial-scan microprocessor

We present our experiences generating scan-based critical-path tests for the partial-scan Alpha 21364 microprocessor, including the effects of crosstalk and multiple-inputs switching on path delay. Insufficient scan penetration made this difficult [D.Bhavsar (2002)], but a new ATPG algorithm increased our coverage. Comparison with actual silicon shows interesting results; we explain them with statistical analysis, factoring the effect of statistical process variation into the effects of crosstalk and multiple-input switching on delay. Finally, we draw conclusions about how to help make future designs amenable to speed testing.

Synchronizing the IEEE 1149.1 test access port for chip level testability

IEEE STD 1149.9 is a widely accepted testability standard in the industry. Although its mandatory provisions focus narrowly on board level assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standards TAP to be used at the system level for general system-level test and maintenance tasks and at the chip level for accessing chip-level testability features. Chip-level applications thus far have used the port for accessing the chips scan design or for simple triggering of on-chip built-in self-test features via the RUNBIST instruction. Applications requiring general access to chipwide testability features that operate at the full chip-clock rate have been rare, primarily because of one of the standards basic tenets-namely, its dedicated test clock. This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features.

Scan Islands - a scan partitioning architecture and its implementation on the Alpha 21364 processor

The paper presents a pragmatic scan partitioning architecture that allows less than perfect scan design in high performance, VLSI circuits to cost-effectively achieve test development and manufacturing test goals. The paper then describes an implementation of the architecture on Compaqs Alpha 21364 microprocessor.

Scan wheel-a technique for interfacing a high speed scan-path with a slow speed tester

A novel interface architecture allows slow-speed test equipment to control and access scan registers operating at the full clock rate of the chip or the system. The architecture requires simple on-chip hardware and works with a minimal number of chip pins.

Test access and the testability features of the Poulson multi-core Intel Itanium® processor

This paper presents the “t-Ring” based DFX access architecture and the testability features of Intels latest multi-core Itanium® processor. The architecture solves many common challenges of testing a multi-core CPU using distinctive and innovative solutions. At the core of the architecture is a hierarchical and scalable test access mechanism design providing flexible access for a variety of use models in high volume manufacturing test and debug platforms.