Joel Grodstein

Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems

Debugging and speed-binning a fabricated design requires a pattern-dependent timing model to generate patterns, which static timing analysis is incapable of providing. To address these issues, we propose a timing analysis tool that integrates a pattern-dependent delay model into its analysis. Our approach solves for the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a satisfiability (SAT) solver. We generate a critical path and input vectors that stimulate it, taking into account pattern-dependent effects such as data-dependent gate delays and multiple-inputs switching. The effectiveness and validity of the proposed methodology is illustrated through experiments on various benchmark circuits and comparisons directly with SPICE.

Automatic generation of critical-path tests for a partial-scan microprocessor

We present our experiences generating scan-based critical-path tests for the partial-scan Alpha 21364 microprocessor, including the effects of crosstalk and multiple-inputs switching on path delay. Insufficient scan penetration made this difficult [D.Bhavsar (2002)], but a new ATPG algorithm increased our coverage. Comparison with actual silicon shows interesting results; we explain them with statistical analysis, factoring the effect of statistical process variation into the effects of crosstalk and multiple-input switching on delay. Finally, we draw conclusions about how to help make future designs amenable to speed testing.

RESTA: a robust and extendable symbolic timing analysis tool

Successful timing analysis for high-speed integrated circuits requires accurate delay computation. However, full-custom circuits popular in todays CPU designs make this difficult. A good circuit-level static timing analysis tool should 1) consider both internally or externally specified input constraints; 2) handle a wide range of circuit structures; and 3) have a robust underlying framework that can be applied independent of the actual device model. In this paper, we present RESTA, a Robust and Extendable Symbolic Timing Analysis tool that aims to address these three goals. RESTA estimates the delay for all valid input assignments, while naturally handling input constraints. We start with a simple linear resistor model for transistors and from there apply various heuristics to improve the delay estimation for the circuits without altering the symbolic algorithms. Our worst-case delay estimates are within 10% of SPICE for over 90% of the circuits we simulated.

Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU

A 1.75 MByte L2 cache has been designed and fabricated as part of the Alpha 21364 microprocessor[1] (Figure 1), in a .18m bulk CMOS process. The cache was designed to run at 1.2 GHz, and pass-1 samples confirm this. While Alpha CPUs are known primarily for high speed, the combination of package constraints and a tight schedule forced careful attention to the integrated whole of power expenditure and the interaction of CAD with design. The cache consumes only 7% of total die power.

Static race verification for networks with reconvergent clocks

We introduce a new method for pruning combinational paths in a static timing verifier. Our method is fast and robust, even for networks with min-max delays on reconvergent clock trees. We will show that current techniques for static timing verification are either not robust or not efficient for such networks. We will also show that these networks are becoming increasingly important with newer low-power, high-speed integrated circuits. We propose a new pruning strategy for such networks which is both correct and efficient.