Dima Kilani

Adaptive zero-crossing digital phase-locked loop for packet synchronization

This paper describes the design and performance analysis of a new approach for frequencysynchronization and transfer over packet networks. The proposed system utilizestimestamps-based with raised cosine pulse shaping first order adaptive zero-crossing digital phase-locked loop (AZC-DPLL). The system is designedto recover frequency as well as packets, independently of the input signal level in the presence of noise. This technique provides reliable locking by adjusting the loop gain, with the aid of finite state machine (FSM), and hence both system locking range and acquisition are improved.

An Efficient Switched-Capacitor DC-DC Buck Converter for Self-Powered Wearable Electronics

This paper introduces an efficient reconfigurable, multiple voltage gain switched-capacitor dc-dc buck converter as part of a power management unit for wearable electronics. The proposed switched-capacitor converter has an input voltage of 0.6 V to 1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated output voltage levels, namely 1 V, 0.8 V, and 0.6 V based on two reconfigurable bits over a wide range of load currents from 10 μA to 800 μA. The switched-capacitor converter is designed and fabricated in 65-nm low-power CMOS technology and occupies an area of 0.493 mm2. The design utilizes a stack of MIM and MOS capacitances to optimize the circuit area and efficiency. The measured peak efficiency is 80% at a load current of 800 μA and regulated load voltage of 1 V.

Switched capacitor DC-DC converter for ultra-low power applications

This paper presents a reconfigurable high efficiency Switched Capacitor DC-DC Converter targeting ultra-low power applications. The Switched Capacitor utilizes multiple gains to provide variable output voltage (1V, 0.8V and 0.6V). The design modulates both switching frequency and transistor size depending on the load current in order to minimize the losses associated with the Switched Capacitor. The Switched Capacitor is implemented using 65nm Low Power CMOS process technology, spice simulation shows power efficiency above 65% over a wide range of load current from 10 μA to 1mA. The power efficiency reaches its peak value of 85% at low load current of 500 μA.

LDO regulator versus switched inductor DC-DC converter

DC-DC converters are important building block of most of todays System-on-Chips (SoCs). This is true because the need to modulate the voltage of different parts of the chip to operate at the optimum level is essential to achieve high power efficiency. This paper investigates two topologies of the DC-DC converter that are widely used. The two topologies are Low Dropout regulator and Switched Inductor DC-DC buck converter. The operation for both topologies is explained as well as the advantages and disadvantages of each topology. Spice simulation with 65nm low power foundry process technology is used to compare the two topologies in terms of energy efficiency, settling time, area, and design complexity. Detail study of voltage level conversion and output load current and its impact on efficiency is also reported.

An efficient thermal energy harvesting and power management for μWatt wearable BioChips

This paper presents an efficient thermal energy harvesting IC (EHIC) that supports a battery-less μWatt system-on-chips. The EHIC consists of an inductor-based DC-DC converter that boosts a low input voltage to a suitable output voltage level. Further, a switched capacitor buck converter is utilized to regulate the boost converter output voltage and to support multiple output voltage levels, namely 0.6V, 0.8V and 1V. In low energy mode and to enhance the efficiency, the EHIC is capable of bypassing the switched capacitor so that the load is driven directly from the boost converter. The prototype chip is fabricated in 65nm CMOS and occupies an area of less than 0.46mm2. Measured results confirm an efficiency of 65% at 0.6V output voltage and 42μW. In addition, the end-to-end peak efficiency is 71% at 0.8V output voltage and 182μW.

An 83% efficiency, 0.6V to 1V output switched-capacitor DC-DC converter for micro-watt power applications

This paper presents an efficient on-chip switched-capacitor DC-DC buck converter targeting μW power range applications. The proposed switched-capacitor converter has an input of 1.2V and generates multiple output voltage levels, namely 1V, 0.8V and 0.6V based on two digital bits. In addition, the switched-capacitor converter has the capability to drive a wide range of load currents from 10μA to 800μA that is set by the operating frequency. The proposed converter is designed and fabricated in 65nm low power CMOS technology and occupies an area of 0.43mm2. The design utilizes both MIM and MOS capacitances stacked above each other so that the system area and efficiency are optimized. The measured maximum power efficiency from silicon is 83% for a load current of 400μA at 0.8V.

An efficient power management unit for μWatt thermoelectric generators

This paper presents an efficient power management unit (PMU) that supports μWatt load range for TEG-based applications. The PMU consists of an inductor-based DC-DC converter that boosts a small TEG voltage and followed by two switched capacitor-based buck converters which are used to drive a μWatt-SoC. The PMU generates a regulated 1.1V and 0.6V output voltages. Pulse frequency modulation scheme is utilized to regulate the output voltages. SPICE simulation results in 65nm CMOS technology show that the maximum end-to-end efficiency of the PMU is 68% at an output power of 62μWatt. The PMU occupies an area of less than 0.9mm2. The switched capacitor circuit enables the usage of dynamic voltage scaling (DVS) that helps the PMU to operate in ultra-low power modes.

Digital pulse frequency modulation for switched capacitor DC-DC converter on 65nm process

DC-DC converter is one of the most important building blocks in any System-on-Chip (SoC). DC-DC converter has the functional capabilities to supply various voltage levels to various loads of the chip in a way to achieve high power efficiency. Pulse Frequency Modulation is considered as the main control technique for voltage regulation of the Switched Capacitor DC-DC power converter. This paper proposes a design of a digital Pulse Frequency Modulation using Verilog-HDL and verified on 65nm low power process technology. The design includes the generation of the non-overlapping clock by the ring oscillator and the dead time circuit instead of the default clock. PFM has a total power of 7μW, area of 46.4μm2 and a slack time of 0.5ns.

Self-Powered SoC Platform for Wearable Health Care

This chapter presents a top-level design of the first self-powered SoC platform that can predict, with high accuracy, ventricular arrhythmia before it occurs. The system provides a very high level of integration in a single chip of mainstream modules that are typically needed to build biomedical devices. Hence, the platform could help in reducing the cost in designing not only for ECG monitoring systems, but for generic low-power health care devices. The platform consists of a graphene-based sensors to acquire ECG signals, an analog front-end to amplify and digitize the ECG, a custom processor to perform feature extraction and classification, a wireless transmitter to send the data to a point of care, and an energy harvesting unit to power the whole system. The platform consumes very low power that can be completely powered by the thermal energy generated from the human body. The system is imagined to be integrated within a necklace which can be worn by a patient comfortably. Hence, it can provide a continuous monitoring of the patient’s condition and connect him directly to his doctor for immediate attention if necessary.

Reconfigurable, Switched-Capacitor Power Converter for IoT

This chapter introduces an efficient reconfigurable, multiple voltage gain switched-capacitor DC–DC buck converter as part of a power management unit for wearable IoTs. The switched-capacitor converter has an input voltage of 0.6–1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated output voltage levels, namely 1, 0.8 and 0.6 V based on two reconfigurable bits over a wide range of load currents from 10 \(\upmu \)A to 800 \(\upmu \)A. The switched-capacitor converter is designed and fabricated in 65 nm low-power CMOS technology and occupies an area of 0.493 mm\(^2\). The design utilizes a stack of MIM and MOS capacitances to optimize the circuit area and efficiency. The measured peak efficiency is 80\(\%\) at a load current of 800 \(\upmu \)A and regulated load voltage of 1 V.