Dimitri Kagaris

Maximum weighted independent sets on transitive graphs and applications

We present a polynomial-time algorithm that finds the maximum weighted independent set of a transitive graph. The studied problem finds applications in a variety of VLSI contexts, including path delay fault testing, scheduling in high-level synthesis, and channel routing in physical design automation. The algorithm has been implemented and incorporated in a CAD tool for path delay fault testing. We experimentally verify its impact in the latter context.

A Hamming distance based test pattern generator with improved fault coverage

This paper proposes a new test pattern generator (TPG) which is an enhancement of GLFSR (Galois LFSR). This design is based on certain non-binary error detecting codes, formulated over an extension field of GF(2/sup /spl delta//), /spl delta/ > 1. The resulting generator provides a guaranteed Hamming distance between successive test patterns, resulting in shorter test lengths. As an additional advantage, the proposed TPG has the intrinsic ability to detect 1-bit errors in the TPG itself. Detailed design methodology and experimental results are presented. The results presented here also have implications in algebraic coding theory in that they may lead to new coding techniques for test pattern generation.

A similarity transform for linear finite state machines

A practical algorithm in terms of ease of implementation and speed is presented to find a similarity transform between any two similar linear finite state machines (LFSMs). The transform is based on the extemal-XOR LFSR companion matrix instead of the more usual internal-XOR LFSR companion matrix. The complexity of the algorithm amounts to that of inverting an n × n matrix, where n is the LFSM size.

Built-in TPG with designed phaseshifts

In this paper, we present built-in test pattern generation (TPG) mechanisms that can enforce a prescribed exact set of phaseshifts, or channel separations, on the bit sequences produced by their successive stages, while still requiring low hardware overhead. Such mechanisms are used in controlling the amount of correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive TPG in a two-dimensional TPG architecture. The reduction in hardware overhead is achieved by a new technique that merges the logic of the original TPG mechanism with that of the required phase shifter network in order to yield an improved compact structure.

Minimizing Observation Points for Fault Location

We investigate the benefit of inserting observation points in a circuit in order to improve its diagnostic resolution. The insertion of the points is done so that each fault has a unique signature on these points under at least one of the applied test patterns. The observation points are scan-like elements that serve as test-phase outputs and can be organized in and observed through one or multiple chains. Experimental results show good tradeoffs between number of observation points that need to be inserted and diagnostic resolution achieved.

Multiple-seed TPG structures

Linear feedback shift registers (LFSRs) are popular mechanisms for built-in test pattern generation (TPG). They are normally used with a primitive characteristic polynomial because, in that case, only one initialization state (seed) is required. We show that if the characteristic polynomial is nonprimitive irreducible, the required seeds can still be efficiently generated. We establish a formula that shows how the seeds of any nonprimitive irreducible polynomial relate to each other. This leads to an efficient hardware implementation with small hardware overhead, irrespective of the number of seeds, and enhances the choices available for the design of appropriate TPG structures in the case of pseudoexhaustive TPG that were previously limited to primitive characteristic polynomials only.

Transistor-Level Synthesis for Low-Power Applications

An important factor which greatly affects the power consumption and the delay of a circuit is the input capacitance of its gates. High input capacitances increase the power consumption as well as the time for charging and discharging the inputs. Current approaches address this problem either through gate-level only resynthesis and optimization, or indirectly through transistor-level synthesis aimed for transistor count reduction. In this paper a method is presented to synthesize complex gates at the transistor level with explicit consideration of the switching activity profile for the gate. The method finds a power efficient implementation by giving priority to transistor inputs with higher switching activity, while keeping the overall number of required transistors low. Experimental results demonstrate the benefit of the approach

LFSR Reseeding with Irreducible Polynomials

We propose an innovative scheme for LFSR re- seeding based on the efficient generation of the seeds of any non-primitive irreducible polynomial. The scheme has very small hardware overhead irrespective of the number of seeds and guarantees that the generation of the pattern subsequence from each seed is disjoint. Experimental results demonstrate the potential of the mechanism for pseudorandom test pattern generation in a parallel chain test-per-scan environment.

InTeRail: a test architecture for core-based SOCs

A flexible test architecture for embedded cores and all interconnects in a system-on chip (SOC) is presented. It targets core testing parallelism and reduced test application time by using, as much as possible, existing core interconnects to form TAM paths. It also provides for dynamic wrapper reconfiguration. Algorithms that minimize the use of extra interconnects for the TAM path formation are presented and evaluated.

Towards optimal design of avionics networking infrastructures

In this work, we address the problem of transforming the process of making design decisions for networking infrastructures in avionics systems from an ad-hoc approach to a systematic, structured approach. Given a set of data communications needs, the goal is to show how a variety of candidate network topologies (e.g. multi-drop bus vs. hub-and-spoke) and avionics protocols such as ARINC 664, MIL-STD-1553B, ARINC 429 and ARINC 825 (CAN), would perform over a continuum of values, and select the best configuration for a given target platform. We have developed a simulation tool based on OPNET which (a) emulates each of the above standards (b) identifies strengths and limitations of each one in handling a given load and characterizes their behavior over a continuum of values, and (c) provides guidelines for the optimal choice to meet the given requirements.