Spyros Tragoudas

ATPG for path delay faults without path enumeration

We present a new ATPG methodology for detecting path delay faults in combinational circuits. The proposed approach is non-enumerative and generates a small number of test patterns with high fault coverage. A new ATPG framework for path delay faults is introduced; it collapses the two phases (path sensitization and line justification) of traditional ATPGs into one. The proposed framework utilizes both structural and functional techniques. A BDD-based implementation and experimentation with the ISCAS85 benchmarks shows that the proposed method outperforms all ATPG methods that bound the test set. The results also show that the approach is comparable to existing ATPG methods that do not bound the test set.

ATPG tools for delay faults at the functional level

We propose and evaluate two frameworks for functional level ATPG for delay faults in combinational circuits. Although functional delay fault models have been recently proposed [9, 13, 10], no systematic methodologies for ATPG have been presented in the literature. The proposed frameworks apply to any proposed fault model, and utilize established techniques such as Reduced Ordered Binary Decision Diagrams (ROBDDs) and Boolean Satis ability (SAT).

Transmissions in a Network with Capacities and Delays

We examine the problem of transmitting in minimum time a given amount of data between a source and a destination in a network with finite channel capacities and nonzero propagation delays. In the absence of delays, the problem has been shown to be solvable in polynomial time. In this paper, we show that the general problem is NP-complete. In addition, we examine transmissions along a single path, called the quickest path, and present algorithms for general and special classes of networks that improve upon previous approaches. The first dynamic algorithm for the quickest path problem is also given.

Accurate path delay fault coverage is feasible

We examine the problem of determining the exact number of path delay faults that a given set of p pairs of patterns detects in a combinational circuit consisting of I lines. Several fault coverage pessimistic heuristics and exact algorithms with worst case exponential behavior have been recently presented with trade-offs between the quality of fault coverage and the time performance. None of the existing approaches has provably good performance. This paper presents the first polynomial time algorithms that calculate the path delay fault coverage exactly. Experimental results on the ISCAS85 benchmarks demonstrate the effectiveness of the presented approaches.

Maximum weighted independent sets on transitive graphs and applications

We present a polynomial-time algorithm that finds the maximum weighted independent set of a transitive graph. The studied problem finds applications in a variety of VLSI contexts, including path delay fault testing, scheduling in high-level synthesis, and channel routing in physical design automation. The algorithm has been implemented and incorporated in a CAD tool for path delay fault testing. We experimentally verify its impact in the latter context.

A fast nonenumerative automatic test pattern generator for path delay faults

This paper presents a nonenumerative automatic test pattern generator for robustly testable path delay faults. In contrast to earlier work by I. Pomeranz, et al. (see IEEE Trans. Computer-Aided Design, vol. 14, p. 1505-15, Dec. 1995), the pattern generator takes into consideration the conditions for robust propagation while sensitizing sets of paths. This increases the probability of testing them robustly with a single test. Novel algorithms are described which identify sets that contain many such potentially compatible paths. The number of detected faults is estimated using a simple and fast method. The approach compares favorably to that of Pomeranz et al. in both fault detection and time performance.

Testing for path delay faults using test points

Path delay fault testing is often difficult due to the large number of paths that must be tested. Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of paths that need to be tested in a circuit. Test points allow the tester to test subpaths of the circuit and then draw conclusions of the operability of the circuit based upon the delays of subpaths. We illustrate some of the limitations of current subpath testing procedures and illustrate some of the difficulties associated with unstructured test point placement. We give an implementation of test points embedded in a scan chain and present a new testing technique that is more accurate than the previous method. We also present a novel test point insertion approach that has reasonable test times and minimal impact on the hardware size and the operational clock.

Generation of hazard identification functions

We study the problem of identifying the complete set of pairs of input patterns that can cause different types of hazards to appear at a circuit line. A novel methodology to implicitly identify all possible input configurations is proposed. The technique is based on a systematic derivation of the conditions for the occurrence of static and dynamic hazards at a line, which are subsequently formulated as Boolean functions defined over variables representing the primary input signals. Our experimental results demonstrate that the proposed approach is very promising and outperforms existing approaches. In addition, they show that a proposed solution for the decision problem of hazard existence at a circuit line is very efficient.

The most reliable data path transmission

We examine the problem of transmitting a units of data in the most reliable manner along an (s,t) path of a network N=(V,E,c,d,r,s,t). Each edge of a network is assigned a capacity, a delay and a reliability value. In contrast to the similarly defined shortest path problem, it is shown that for this more complex routing problem the subpaths of an optimal path are not necessarily optimal. However, an optimal polynomial is presented. On acyclic networks with interconnections that operate with the same reliability probability, we present a polynomial time algorithm that computes the best route for each value of /spl sigma/. This is a very useful precomputation when different amount of data need to be transmitted at different time periods.

Functions for quality transition fault tests

The paper shows how to generate a function that contains all possible tests to detect a transition fault. Moreover, a systematic methodology is presented that derives the functions for all transition faults based on only two circuit traversals. Quality tests are generated by requiring that the function formulation considers established sensitization criteria to either activate a transition at the fault site or propagate it to a circuit output. Experimental results on the ISCAS85 and ISCAS89 benchmarks demonstrate the promise of the method which can also lead to efficient compaction methods for transition faults.