Dirk C. Jordan

Mechanism of cleaning Si(100) surface using Sr or SrO for the growth of crystalline SrTiO3 films

A method for removing SiO2 and producing an ordered Si(100) surface using Sr or SrO has been developed. In this technique, a few monolayers of Sr or SrO are deposited onto the as-received Si(100) wafer in an ultrahigh vacuum molecular-beam epitaxy system. The substrate is then heated to ∼800 °C for about 5 min, the SiO2 is removed to leave behind a Sr- or SrO-terminated ordered Si(100) surface. This Sr- or SrO-terminated Si(100) surface is well suited for the growth of crystalline high-k dielectric SrTiO3 films. Temperature programmed desorption measurements were carried out to understand the mechanism of removing SiO2 from Si(100) using Sr or SrO. The species we observed coming off the surface during the temperature cycle were mainly SiO and O, no significant amount of Sr containing species was observed. We conclude that the SiO2 removal is due to the catalytic reaction SiO2+Sr(or SrO)→SiO(g)+O+Sr(or SrO). The reaction SiO2+Si→2SiO(g) at the SiO2/Si interface is limited and the pit formation is suppressed. The main roles that Sr or SrO play during the oxide removal process are catalysts promoting SiO formation and passivating the newly exposed Si surface, preventing further etching and the formation of pits in the substrate.A method for removing SiO2 and producing an ordered Si(100) surface using Sr or SrO has been developed. In this technique, a few monolayers of Sr or SrO are deposited onto the as-received Si(100) wafer in an ultrahigh vacuum molecular-beam epitaxy system. The substrate is then heated to ∼800 °C for about 5 min, the SiO2 is removed to leave behind a Sr- or SrO-terminated ordered Si(100) surface. This Sr- or SrO-terminated Si(100) surface is well suited for the growth of crystalline high-k dielectric SrTiO3 films. Temperature programmed desorption measurements were carried out to understand the mechanism of removing SiO2 from Si(100) using Sr or SrO. The species we observed coming off the surface during the temperature cycle were mainly SiO and O, no significant amount of Sr containing species was observed. We conclude that the SiO2 removal is due to the catalytic reaction SiO2+Sr(or SrO)→SiO(g)+O+Sr(or SrO). The reaction SiO2+Si→2SiO(g) at the SiO2/Si interface is limited and the pit formation is suppresse...

63.2: High Brightness, High Voltage Color Field Emission Display Technology

We have designed nanotube-based field emission displays to operate above 6500 V. As a result, we have improved the white-screen luminance of HDTV resolution (0.726 mm pixel) field emission displays beyond 700 cd/m2. We have maintained good color purity without employing separate focusing electrodes. In addition, we demonstrate spacers operating beyond 10,000 volts on the anode without any charging that would distort the image.

Dynamic studies on the charging of spacers for high-voltage field-emission displays

— In this article, a systematic study on the relationship between the rate of spacer surface-charge accumulation and the anode voltages in a dynamic setting is presented. The spacers are placed in a test package simulating a field-emission panel where electron trajectories are recorded along a preset timeline. True secondary emission of spacers under the influence of an anode field is then deduced and the factors affecting the rate of charge accumulation on the spacer surface are discussed. The results of invisible spacers under different operating conditions of anode voltage, emission current, and pulse width will also be given.

Progress in Epitaxial Oxides on Semiconductors

In this paper, we review the recent progress in the area of epitaxial oxides on semiconductors at Motorola Labs. Critical issues such as surface preparation, initial nucleation and growth behaviors of SrTiO 3 (STO) thin film epitaxy on Si(001) are addressed. Using a systematic approach, high-quality epitaxial STO films are successfully grown on semiconductor substrates such as Si, silicon-on-insulator (SOI) and Ge. Amorphous interfacial layer between the epitaxial STO and the semiconductor can be eliminated or tailored by controlling oxide growth process and parameters. STO-based metal-oxide-semiconductor (MOS) capacitors and transistors are fabricated and tested, in order to explore the potential of STO as high-k gate dielectrics for future generation CMOS transistor technology. In addition, high-quality STO epitaxial films are utilized as thin buffer layers for fabricating integrated oxide heterostructures on semiconductors. Various perovskite oxide films such as SrZrO 3 , LaAlO 3 and Pb(Zr,Ti)O 3 are deposited epitaxially on STO-buffered Si(001) for potential high-k gate dielectrics and surface-acoustic-wave (SAW) device applications.

Development of integrated heterostructures on silicon by MBE

The semiconductor industry is facing the challenge of scaling of the gate dielectric of Si CMOS devices, which are continually being made smaller. Presently SiO/sub 2/ is being used, but at thickness below 20/spl Aring/, it suffers from high tunneling leakage current and reliability problems. Alternative high-k materials to replace SiO/sub 2/ need to be developed as soon as possible. The alkaline earth oxides such as barium strontium titanate (Ba/sub x/Sr/sub 1-x/TiO/sub 3/) have a substantially higher dielectric constant and are ideal candidates for gate dielectrics. Because of the higher dielectric constant a physically thicker layer can yield an equivalent oxide thickness of <20/spl Aring/, thereby eliminating the leakage problems experienced with ultra-thin SiO/sub 2/. These oxides also exhibit ferroelectric behavior and their use as the gate dielectric on Si can be exploited in the realization of a single transistor memory element. These types of oxides also have a number of functionalities which when combined with other types of semiconductors will enable the development of novel device applications. Molecular beam epitaxy can be used for the deposition of oxide based epitaxial layers both for Si device applications and integration of GaAs devices with silicon. The potential for increased functionality and integration of devices based on III-V semiconductors, crystalline oxides and silicon make this an attractive and promising technology.