Dirk Schweitzer

Transient Measurement of the Junction-To-Case Thermal Resistance Using Structure Functions: Chances and Limits

The accurate and reproducible measurement of the junction-to-case thermal resistance Rth-JC of power semiconductor devices is far from trivial. In the recent time several new approaches to measure the Rth-JC have been suggested, among them transient measurements with different interface materials between the package and a heat-sink which allow identifying the Rth-IC in the structure function of the heat flow path. This paper shows that numerical effects during the calculation of the structure function as well as 3D heat spreading have a big influence on the structure function which makes it often difficult to determine the Rth-IC. Finite element simulations can provide a clue to identify this value in the structure function. The theoretical findings are applied to and demonstrated for actual measurements and the new approach is compared to the traditional method (involving a thermo-couple measurement of the case temperature) with respect to accuracy and reproducibility. Finally an alternative approach to determining the Rth-IC from transient dual- interface measurements, which is not based on structure functions, is presented.

The junction-to-case thermal resistance: A boundary condition dependent thermal metric

Contrary to popular belief the junction-to-case thermal resistance (Rth-JC) of a power semiconductor is not an intrinsic property of the device but depends to some extend on the cooling condition at the case surface intended for heat sinking. In addition to this the Rth-JC can be measured only with quite limited accuracy by the methods existing today. This paper investigates the dependence of the Rth-JC of power packages on different cooling conditions and tries to give an assessment of the accuracy of two measurement methods: the traditional method using a thermocouple to measure the case temperature versus the recently proposed transient dual interface method. Consequences and limits for the use of the junction-to-case thermal resistance in engineering applications as well as for standardization issues are discussed.

Transient dual interface measurement — A new JEDEC standard for the measurement of the junction-to-case thermal resistance

The junction-to-case thermal resistance Rth-JC is an important thermal characteristic for power semiconductor devices. Its value is often one of the main criteria for the decision whether a device can be used in a thermally demanding environment, and a low Rth-JC therefore is a competitive advantage for the semiconductor manufacturer. On the other hand the vendors must ensure that their data-sheet values do not underestimate the actual Rth-JC values. Hence accurate and reproducible methods to measure the Rth-JC are required. Unfortunately these requirements are not easy to meet, which is reflected by the fact that until very recently there existed no JEDEC industry standard for the determination of this thermal metric. During the last three years we have intensely tested and further developed a new transient measurement method for the Rth-JC of power semiconductor packages with a single heat flow path. The so called transient dual interface measurement (TDIM) which allows measuring the Rth-JC with higher accuracy and better reproducibility than traditional methods has now been accepted as JEDEC standard JESD51–14.

Thermal transient modeling and experimental validation in the European project PROFIT

Results of the European project PROFIT on thermal transient measurement and modeling of IC packages are presented. All together 16 different packages from the three semiconductor manufacturers Infineon, Philips and ST Microelectronics were measured in four dual cold plate (DCP) environments as defined in the preceding DELPHI and SEED projects. Solutions to measure TO-type and fine pitch packages in the DCP, especially for the critical DCP-4 boundary condition were demonstrated, as well as reduction of interface resistance and increased reproducibility by using Woods alloy as an interface material. The measurements were simulated using the commercial software packages ANSYS/spl reg/, FLOTHERM/spl reg/ or MARC/spl reg/. The agreement between simulated and measured thermal impedance is quite good (<15%) from steady state (t=1000s) to transients with t<0.1s, i.e. 4 orders of magnitude. In a few cases, this level of accuracy was kept even over 7 orders of magnitude. Increasing relative inaccuracy with shorter transients corresponds to small absolute errors in temperature. So for practical pulse temperature prediction, the accuracy should already be sufficient, for extraction of geometrical and material parameters, it is probably not.A major objective of the European project PROFIT is to generate boundary condition independent (BCI) dynamic compact thermal models (DCTM) of semiconductor products. Extending the methods for steady BCI-CTM developed in preceding projects DELPHI and SEED to the transient domain, a detailed numerical model of the component is needed, which is validated against four dual cold plate (DCP) experiments extracting heat along the main heat flow paths from a package. The validated detailed model is then used for numerical experiments in many environments represented by external BC. Results are used to optimize resistors and capacitors of a small network forming the DCTM. This work is focused on the first part of developing validated detailed dynamic models by comparison of modeling and measurements. Results of the European project PROFIT on thermal transient measurement and modeling of integrated circuit packages are presented. All together sixteen different packages from the three Semiconductor Manufacturers Infineon, Philips, and ST Microelectronics were measured in four DCP environments as defined in the preceding DELPHI and SEED projects. Solutions to measure TO-type and fine pitch packages in the DCP, especially for the critical DCP-4 boundary condition were demonstrated, as well as reduction of interface resistance and increased reproducibility by using Woods alloy as an interface material. The measurements were simulated using the commercial software packages ANSYS, FLOTHERM, or MARC. The agreement between simulated and measured thermal impedance is 15% or better from steady state (t=1000 s) to transients with t>0.1, i.e., four orders of magnitude. In a few cases, this level of accuracy was kept even over seven orders of magnitude. Increasing relative inaccuracy with shorter transients corresponds to small absolute errors in temperature. So practical pulse temperature prediction will usually be correct within a few degrees. Extraction of geometrical and material parameters will need further improvement.

Development of a standard for transient measurement of junction-to-case thermal resistance

The paper summarizes the development of a standard to measure the thermal resistance “junction-to-case” θ<inf>JC</inf> of semiconductor devices with heat flow through a single path. Power switches or amplifiers are typical examples. θ<inf>JC</inf> is a key performance metric to decide whether a device can be used in thermally critical applications. Hence an accurate and reproducible method to measure θ<inf>JC</inf> is required. This is not easy, especially for low θ<inf>JC</inf>, which is reflected by the fact that no JEDEC industry standard existed to measure θ<inf>JC</inf>. During the last four years we have evaluated approaches and developed a new method called Transient Dual Interface (TDI) method. It uses two measurements of the thermal impedance Zth or more specific Z<inf>θJC</inf>(t) of the device with different cooling conditions at the interface of device case and a heat sink. To evaluate these measurements two methods are applied. Method 1 determines θ<inf>JC</inf> directly from the separation of Zth-curves. θ<inf>JC</inf> is the thermal impedance Z<inf>θJC</inf>(ts) at the time ts where the two Z<inf>θJC</inf>(t)-curves separate. Method 2 first calculates cumulative structure functions and uses their separation point to determine θ<inf>JC</inf>. Both data evaluation methods complement each other, because method 1 is most accurate for low θ<inf>JC</inf> in the range of 1K/W or below, while method 2 is more accurate for higher θ<inf>JC</inf> > 1 K/W. The TDI method allows to measure θ<inf>JC</inf> with higher accuracy and better reproducibility than the steady state method used in industrial practice up to now. The TDI method was published as JEDEC standard JESD51-14 in November 2010. Problems of the traditional steady state measurement and main steps of the development of the TDI method are discussed.

Thermal transient characterization of semiconductor devices with multiple heat sources - Fundamentals for a new thermal standard

The thermal performance of semiconductor devices is most often specified according to JEDEC standards JESD51 1-14 which describe precisely how various steady-state thermal metrics are to be measured. Most of these metrics represent a thermal resistance between the junction of a semiconductor and some reference; e.g. Rth-JA (Junction-to-ambient), Rth-JB (Junction-to-board), or Rth-JC (Junction-to-case). However all of the above thermal metrics characterize the steady-state behaviour and have been designed for semiconductors with a single heat source only. While the extension of a stationary thermal resistance Rth-JX to the corresponding transient thermal impedance Zth-JX is straightforward the adaptation of existing standards for the characterization of devices with multiple heat sources is far less obvious. This publication gives an overview on the theoretical framework which allows extending the existing thermal metrics in a compliant way.

Thermal impact of randomly distributed solder voids on Rth-JC of MOSFETs

The work presented applies a statistical approach to study randomly distributed solder voids in MOSFET products. The grid size was varied as independent of the mesh element to account for typical void sizes observed in X-ray images. Thereafter the impact of random voids for different chip sizes was quantified. Results show that higher maximum chip temperatures can occur with voids located in the corner of the die. A simple analytical expression thereafter was developed to understand and explain this. Rth-JC (thermal resistance junction-to-case) and IR (infrared) measurements of selected test devices with known void distribution were performed as well. Measurement and simulated results were compared. In this work we attempt to establish a model for the evaluation of the process impact on Rth-JC. It also leads to some guidelines of solder joint inspection criteria for power devices.

Thermal transient characterization of semiconductor devices with multiple heat sources-Fundamentals for a new thermal standard

The thermal performance of semiconductor devices is most often specified according to JEDEC standards JESD51 1-14 which describe precisely how various steady-state thermal metrics are to be measured. Most of these metrics represent a thermal resistance between the junction of a semiconductor and some reference; e.g. Rth-JA (Junction-to-ambient), Rth-JB (Junction-to-board), or Rth-JC (Junction-to-case). However all of the above thermal metrics characterize the steady-state behaviour and have been designed for semiconductors with a single heat source only. While the extension of a stationary thermal resistance Rth-JX to the corresponding transient thermal impedance Zth-JX is straightforward the adaptation of existing standards for the characterization of devices with multiple heat sources is far less obvious. This publication gives an overview on the theoretical framework which allows extending the existing thermal metrics in a compliant way.

Generation of multisource dynamic compact thermal models by RC-network optimization

This paper describes the generation of dynamic compact thermal models (DCTM) for multi-source semiconductor devices by RC-network optimization. Several state-of-the-art non-linear optimization algorithms are compared with respect to their convergence behavior and accuracy of the generated network models and practical aspects like the numerically efficient solution of the RC-network equations, best-choice of the objective function, and exploitation of device symmetry are discussed. The applicability of the methods presented herein is demonstrated for some multi-chip semiconductor devices.

Thermal characterization of multichip structures

The advances in electronic packaging made it possible to encapsulate several independent semiconductor dice into a single package. In the last decade many packaging configurations are realized which range from the multichip modules to the 3D stack-die structures. Thermal aware design of such structures become complex, though. To understand the thermal behavior of multichip structure containing multiple dissipating elements placed on different dice, the couplings between individual dice have to be characterized. To determine their thermal transfer impedance matrix (TTIM) is a practical way to describe the thermal relations. In this paper we demonstrate the method utilized for TTIM measurements and also show how thermal surroundings (e.g. the PCB the chip is mounted on) affect the thermal relations inside the package. In addition, the temperature dependent non-linearity of the TTIMs is also described.