Heinz Pape

Transient Measurement of the Junction-To-Case Thermal Resistance Using Structure Functions: Chances and Limits

The accurate and reproducible measurement of the junction-to-case thermal resistance Rth-JC of power semiconductor devices is far from trivial. In the recent time several new approaches to measure the Rth-JC have been suggested, among them transient measurements with different interface materials between the package and a heat-sink which allow identifying the Rth-IC in the structure function of the heat flow path. This paper shows that numerical effects during the calculation of the structure function as well as 3D heat spreading have a big influence on the structure function which makes it often difficult to determine the Rth-IC. Finite element simulations can provide a clue to identify this value in the structure function. The theoretical findings are applied to and demonstrated for actual measurements and the new approach is compared to the traditional method (involving a thermo-couple measurement of the case temperature) with respect to accuracy and reproducibility. Finally an alternative approach to determining the Rth-IC from transient dual- interface measurements, which is not based on structure functions, is presented.

Transient dual interface measurement — A new JEDEC standard for the measurement of the junction-to-case thermal resistance

The junction-to-case thermal resistance Rth-JC is an important thermal characteristic for power semiconductor devices. Its value is often one of the main criteria for the decision whether a device can be used in a thermally demanding environment, and a low Rth-JC therefore is a competitive advantage for the semiconductor manufacturer. On the other hand the vendors must ensure that their data-sheet values do not underestimate the actual Rth-JC values. Hence accurate and reproducible methods to measure the Rth-JC are required. Unfortunately these requirements are not easy to meet, which is reflected by the fact that until very recently there existed no JEDEC industry standard for the determination of this thermal metric. During the last three years we have intensely tested and further developed a new transient measurement method for the Rth-JC of power semiconductor packages with a single heat flow path. The so called transient dual interface measurement (TDIM) which allows measuring the Rth-JC with higher accuracy and better reproducibility than traditional methods has now been accepted as JEDEC standard JESD51–14.

Thermal transient modeling and experimental validation in the European project PROFIT

Results of the European project PROFIT on thermal transient measurement and modeling of IC packages are presented. All together 16 different packages from the three semiconductor manufacturers Infineon, Philips and ST Microelectronics were measured in four dual cold plate (DCP) environments as defined in the preceding DELPHI and SEED projects. Solutions to measure TO-type and fine pitch packages in the DCP, especially for the critical DCP-4 boundary condition were demonstrated, as well as reduction of interface resistance and increased reproducibility by using Woods alloy as an interface material. The measurements were simulated using the commercial software packages ANSYS/spl reg/, FLOTHERM/spl reg/ or MARC/spl reg/. The agreement between simulated and measured thermal impedance is quite good (<15%) from steady state (t=1000s) to transients with t<0.1s, i.e. 4 orders of magnitude. In a few cases, this level of accuracy was kept even over 7 orders of magnitude. Increasing relative inaccuracy with shorter transients corresponds to small absolute errors in temperature. So for practical pulse temperature prediction, the accuracy should already be sufficient, for extraction of geometrical and material parameters, it is probably not.A major objective of the European project PROFIT is to generate boundary condition independent (BCI) dynamic compact thermal models (DCTM) of semiconductor products. Extending the methods for steady BCI-CTM developed in preceding projects DELPHI and SEED to the transient domain, a detailed numerical model of the component is needed, which is validated against four dual cold plate (DCP) experiments extracting heat along the main heat flow paths from a package. The validated detailed model is then used for numerical experiments in many environments represented by external BC. Results are used to optimize resistors and capacitors of a small network forming the DCTM. This work is focused on the first part of developing validated detailed dynamic models by comparison of modeling and measurements. Results of the European project PROFIT on thermal transient measurement and modeling of integrated circuit packages are presented. All together sixteen different packages from the three Semiconductor Manufacturers Infineon, Philips, and ST Microelectronics were measured in four DCP environments as defined in the preceding DELPHI and SEED projects. Solutions to measure TO-type and fine pitch packages in the DCP, especially for the critical DCP-4 boundary condition were demonstrated, as well as reduction of interface resistance and increased reproducibility by using Woods alloy as an interface material. The measurements were simulated using the commercial software packages ANSYS, FLOTHERM, or MARC. The agreement between simulated and measured thermal impedance is 15% or better from steady state (t=1000 s) to transients with t>0.1, i.e., four orders of magnitude. In a few cases, this level of accuracy was kept even over seven orders of magnitude. Increasing relative inaccuracy with shorter transients corresponds to small absolute errors in temperature. So practical pulse temperature prediction will usually be correct within a few degrees. Extraction of geometrical and material parameters will need further improvement.

Development of a standard for transient measurement of junction-to-case thermal resistance

The paper summarizes the development of a standard to measure the thermal resistance “junction-to-case” θ<inf>JC</inf> of semiconductor devices with heat flow through a single path. Power switches or amplifiers are typical examples. θ<inf>JC</inf> is a key performance metric to decide whether a device can be used in thermally critical applications. Hence an accurate and reproducible method to measure θ<inf>JC</inf> is required. This is not easy, especially for low θ<inf>JC</inf>, which is reflected by the fact that no JEDEC industry standard existed to measure θ<inf>JC</inf>. During the last four years we have evaluated approaches and developed a new method called Transient Dual Interface (TDI) method. It uses two measurements of the thermal impedance Zth or more specific Z<inf>θJC</inf>(t) of the device with different cooling conditions at the interface of device case and a heat sink. To evaluate these measurements two methods are applied. Method 1 determines θ<inf>JC</inf> directly from the separation of Zth-curves. θ<inf>JC</inf> is the thermal impedance Z<inf>θJC</inf>(ts) at the time ts where the two Z<inf>θJC</inf>(t)-curves separate. Method 2 first calculates cumulative structure functions and uses their separation point to determine θ<inf>JC</inf>. Both data evaluation methods complement each other, because method 1 is most accurate for low θ<inf>JC</inf> in the range of 1K/W or below, while method 2 is more accurate for higher θ<inf>JC</inf> > 1 K/W. The TDI method allows to measure θ<inf>JC</inf> with higher accuracy and better reproducibility than the steady state method used in industrial practice up to now. The TDI method was published as JEDEC standard JESD51-14 in November 2010. Problems of the traditional steady state measurement and main steps of the development of the TDI method are discussed.

Induced delamination of silicon-molding compound interfaces

Interface fracture properties are increasingly requested in electronic packaging, be it for design problems or reliability issues. We demonstrate an induced delamination of the epoxy molding compound and die silicon interface, and propose a mixed mode chisel testing setup (MMC) and its experimental procedure. The MMC addresses several drawbacks of existing methods. The work includes samples from package fabrication processes and the establishing of critical fracture mechanics properties through finite element simulation. The setup allows for the investigation of interfaces at package scale.

Comparative study on solder joint reliability using different FE-models

Two finite-element-analysis (FEA) models, 3D-slice model and 1/8 or octant model, were used to simulate the solder joint reliability of ball grid array (BGA) packages. The solders were treated as Anands viscoplastic material and their fatigue life was estimated by Darveauxs model. Simulation results are compared with some Weibull analysis results of the temperature cycling on board (TCOB) tests. It is confirmed that a big solder resist opening (SRO) and soft solder resist material greatly improves the fatigue life of solder joints. A good correlation of the first failure location between testing and simulation was found by cross-sectioning. Mostly the corner ball in the center matrix failed first. Besides, effects of voids in the solder balls are also discussed and analyzed.

Interfacial strength of Silicon-to-Molding Compound changes with thermal residual stress

As we face higher numbers of material layers in the increasingly complex Microsystems, the rating of layers reliability has to keep pace. Fracture mechanical descriptions are a big qualitative improvement when using simulation for design and reliability support, especially when looking at layer delamination. In order to simulate the interfacial fracture we urgently need to find empirical parameters, because the fracture parameters have to be verified as critical. Such experiments are difficult to carry out at the Silicon-to-Epoxy Molding Compound (EMC) interface. We are now able to do such investigations using the Mixed Mode Chisel (MMC) setup. In this paper we compare results of the Silicon-EMC interface for the in- and exclusion of thermal residual stresses in the simulations. The interface specimens are of package scale and are derived from the embedded wafer level molding process. We find the impact of thermal residual stresses crucial for the validity of fracture toughness values, and show relations to consider when using the MMC setup. We do not find any EMC residuals on the delaminated Silicon surface.

How to fabricate specimens for silicon-to-molding compound interface adhesion measurements

We present a new method to fabricate specimen for interfacial fracture testing. It regards the interface between silicon die and epoxy molding compound (EMC). The crucial element of evaluating interfacial fracture strength is the calculation of critical fracture values. Such values can be obtained analyzing a bimaterial type of sample and by specifically inducing a delamination while monitoring conditions and loads. We use a sandwich type of sample where the epoxy molding compound encloses the silicon die. We give a detailed description of molding specimens using an established transfer molding process that has a sufficiently large cavity available. In order to prevent breakage and related residual stresses we use specific bearings to hold the silicon stripes symmetrically in place. The bearings are made out of cured EMC themselves. The samples did not break and allow for interfacial fracture characterization. For testing the specimens we used the Mixed Mode Chisel (MMC) setup, which is one of the first to at all induce and monitor delamination of the Si-EMC interface.

Thermal impact of randomly distributed solder voids on Rth-JC of MOSFETs

The work presented applies a statistical approach to study randomly distributed solder voids in MOSFET products. The grid size was varied as independent of the mesh element to account for typical void sizes observed in X-ray images. Thereafter the impact of random voids for different chip sizes was quantified. Results show that higher maximum chip temperatures can occur with voids located in the corner of the die. A simple analytical expression thereafter was developed to understand and explain this. Rth-JC (thermal resistance junction-to-case) and IR (infrared) measurements of selected test devices with known void distribution were performed as well. Measurement and simulated results were compared. In this work we attempt to establish a model for the evaluation of the process impact on Rth-JC. It also leads to some guidelines of solder joint inspection criteria for power devices.

Effect of substrate warpage on flip chip BGA thermal stress simulation

In this work, a new empirical method is proposed to incorporate the initial substrate warpage into package stress simulation. As a first step, the bare substrate strip warpage characteristics were mapped. The out-of-plane displacements of the substrate strips were measured as a function of temperature using shadow moiré technique. It was observed that the warpage values of the bare substrate vary predominantly along the length of the strip. Units located at the substrate corners and edges exhibited higher warpage compared to units in the strip center. The higher warpage at units located at the substrate edge could impact the flip chip assembly process and also the stresses at the 1st level interconnect.