Django Trombley

A Physical Understanding of RF Noise in Bulk nMOSFETs With Channel Lengths in the Nanometer Regime

Experimental and simulation results of high-frequency channel noise in MOSFETs with 40-, 80-, and 110- nm gate lengths are presented. The measured dc I-V characteristics can be matched using the drift-diffusion (DD) and hydrodynamic (HD) transport models, both incorporating velocity saturation. The DD model grossly underestimates the measured noise, demonstrating the inadequacy of channel-length modulation and impact ionization to explain the excess noise. The HD model generates higher noise but not enough, showing that introduction of carrier heating is still insufficient to explain the experimental results. The underprediction of noise using the HD model can be mitigated by a suitable choice of the energy relaxation time and saturation velocity; however, simultaneous matching of both noise and dc I-V does not produce satisfactory results. Thus, TCAD simulators are unable to simulate this excess-noise mechanism at this time. Experimental data support that, at 40 nm gate lengths, noise can be described by a shot noise like expression.

Numerical investigation of excess RF channel noise in sub-100 nm MOSFETs

High-frequency simulations of channel-thermal noise in MOSFETs with gate-lengths of 40 nm, 80 nm, and 110 nm are presented. The simulated noise parameter γ is a stronger function of the carrier transport model at shorter gate-lengths. Velocity saturation is necessary to produce a good match between the simulated and measured DC I-V characteristics using either the drift-diffusion or hydrodynamic transport models. However, in the presence of velocity saturation, the simulated noise is insufficient in explaining the observed excess noise. Hence, these physics-based device-level simulations point to the presence of a non-thermal RF noise source in the FET channel.

High-frequency noise measurements on MOSFETs with channel-lengths in sub-100 nm regime

High-Frequency signal and noise measurements on 40 nm, 80 nm, and 110 nm, gate-length MOS transistors are performed. On-wafer measurements of S-parameters up to 18 GHz yield an accurate small-signal RF device model with g2 in excess of 1000 mS/mm. Noise contributions due to gate resistance, substrate resistance, source and drain resistances, substrate current and induced-gate noise are found to be small in comparison with total observed noise. The noise parameter γ is bias dependent and increases as channel-length decreases. The observed values are well above the ideal value of 2/3 consistent with previously published results.

A 25 mV-startup cold start system with on-chip magnetics for thermal energy harvesting

Thermal energy harvesting systems use boost converters for high-efficiency low voltage operation, but lack the ability for low voltage startup without off-chip transformers. We present a cold start system that uses integrated magnetics instead of external transformers in a Meissner Oscillator to start up from ultra low voltages, with a switched capacitor DC-DC circuit for additional voltage gain. The oscillator analysis with on-chip magnetics allows device co-optimization for low voltage operation, despite 1000x lower inductance values than off-chip transformers. Co-optimized on-chip transformer and depletion-mode NMOS start up from 25 mV driven directly by a sourcemeter, or 50 mV with a 4.7 Ω series resistance, for the lowest integrated electrical startup. The co-packaged system provides proof of concept for integration with boost converter circuits on a single die to have a fully-integrated low voltage startup solution for thermal energy harvesting applications, without using off-chip transformers.

A novel and accurate methodology for design and characterization of wire-bond package performance for 5–10GHz applications

This paper presents novel and accurate design, simulation and measurement methodologies to characterize high-speed (5-10GHz) signal-path applications on standard Quad-Flat No-leads package (QFN) and Ball Grid Array (BGA) packages. The design of Integrated Circuit (IC) packages and Printed Circuit Boards (PCBs) for high-speed communication (10Gbps+ data-rates) enabling consumer applications is aggressively driven by performance focus while meeting Time-To-Market (TTM) schedules to gain competitive advantage in the market. As a result, such designs demand a carefully verified design strategy for incorporating standard packaging technologies (such as QFN packages) in the high-performance space. This requires going beyond design, simulation and measurement “best-practices” for first-pass success, given that there is little “marginality/specification headroom” available in the electrical performance of simple packaging technologies. Additionally, stringent TTM pressures present another constraint of having to achieve “first-pass system functionality” in a short design cycle. Such requirements of design performance and cycle time demand the need to establish novel design, simulation and characterization frameworks which is the main theme of this paper. Additionally, excellent model-to-hardware correlation has been demonstrated in the paper to establish the accuracy of the proposed modeling and characterization methodologies.