R. P. Jindal

Compact Noise Models for MOSFETs

A physical understanding of both intrinsic and extrinsic noise mechanisms in a MOSFET is developed. Intrinsic noise mechanisms fundamental to device operation include channel thermal noise, induced gate noise, and induced substrate noise. While the effect of channel thermal noise is observable at zero drain-to-source voltage, the induced gate and substrate noise do not manifest themselves under these conditions. However, the attendant fluctuations in the channel charge are observable by the passage of electric current through the device. Extrinsic noise mechanisms manifested due to structural evolution of the MOSFET include the distributed gate resistance noise, distributed substrate resistance noise, bulk charge effects, substrate current supershot noise, gate current noise, excess channel noise, and 1/f noise. Where available, compact noise models covering these noise mechanisms are explained. Also, where possible, methods of suppression of these mechanisms are highlighted. A survey of current public domain MOS models is presented, and a lack of comprehensive coverage of noise models is noted. Open areas of MOSFET noise research in the sub-hundred-nanometer regime are also highlighted. With suitable adaptation, noise concepts elucidated in the context of MOS transistors have a much wider applicability to the operation of HEMTs, JFETs, MESFETs, and other field-effect devices

Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS

The design and test results of a single-chip NMOS automatic gain control (AGC) amplifier are described. The amplifier has a maximum flat gain of 50 dB, dynamic range of 70 dB, and a noise figure of 11 dB. The flat response from near DC to a 3-dB bandwidth of 1 GHz does not require tuning of any peaking circuits. The chip is also capable of operating at 3 GHz with unity gain delivering -8 dBm into a 50-/spl Omega/ load. The global feedback scheme designed for this chip stabilizes it against large shifts in threshold voltage and ambient temperature variation of 170/spl deg/C. This feedback scheme can provide stable DC feedback for a forward amplifier gain of at least 60 dB. Application of this application in the design of low-noise high-speed fibre-optic systems is envisaged.

Phonon fluctuation model for flicker noise in elemental semiconductors

Acoustic mode lattice scattering plays an important role in determining the carrier mobility in elemental semiconductors over a wide range of temperature. For germanium and silicon, over the temperature range of interest, these longitudinal acoustic phonons are primarily scattered by isotopes and chemical impurities. The relaxation time is directly proportional to the fourth power of the phonon wavelength. Hence, for a relatively small phonon wavelength spread of three decades, the phonon relaxation time spans full 12 decades. The number of phonons for a given acoustic mode fluctuates at random. Hence, the phonon population for each mode exhibits a g‐r noise spectrum characterized by its relaxation time. Through electron‐phonon interaction (assuming elastic scattering), this g‐r noise spectrum is transferred to electron mean free path (same holds for hole), where after superposition, it leads to 1/f spectrum. The theoretical results support the experimental findings of several authors.

Noise associated with distributed resistance of MOSFET gate structures in integrated circuits

The effect of thermal voltage fluctuations in a resistive gate matrix perpendicular to the direction of channel current, in a MOSFET, are treated in detail. A general formula is derived to arrive at channel current fluctuations for an arbitrary gate matrix layout. This formulation is an extension of the analysis done by Thornber and is valid for frequencies at which the distributed RC time constants associated with the gate matrix are not important. The results of this analysis can be used to design low-noise resistive gate structures.

Hot-electron effects on channel thermal noise in fine-line NMOS field-effect transistors

Submicrometer NMOSFETs exhibit excess channel thermal noise. This excess noise increases with an increase in drain-to-source voltage and a decrease in channel length. A strong correlation between high electric field and excess noise strongly suggests hot electrons as being responsible for this excess noise.

High frequency noise in fine line NMOS field effect transistors

Noise mechanisms that limit the high frequency performance of submicron channel length NMOS FETs are presented. We develop here a physical understanding of the various noise mechanisms and evaluate the impact of device structure on them. This involves a review of some already published work and an examination of some new results.

Distributed substrate resistance noise in fine-line NMOS field-effect transistors

Thermal noise voltage across the distributed substrate resistance induces a fluctuating substrate potential. These random variations couple to the FET channel, giving rise to fluctuations in the channel current. For devices built on epi substrates, this adds 25 percent more noise power to that already existing due to channel thermal noise. More, compact device layouts for high-frequency applications will result in an increase in this noise source. The situation can be partly rectified by using a thinner and less lightly doped epi material.

Carrier fluctuation noise in a MOSFET channel due to traps in the oxide

Abstract If for a section Δx of a MOSFET channel δN t is the fluctuation in the number of trapped carriers and δN the corresponding fluctuation in the number of carriers in the channel, then S δN ( f ) = S δNt ( f ) ( δN / δN t ) 2 . We have here evaluated — δN / δN t from first principles and compared the results with those obtained by other investigators. It turns out that — δN / δN t is unity for very strong inversion and that it decreases to an extremely small value at very weak inversion.

IIIB-4 noise associated with substrate current in fine-line NMOS field-effect transistors

The noise manifested by impact-ionization-generated substrate current in fine-line NMOS transistors is studied. It is found that this noise can be considerably above the shot noise level for high drain voltages. The magnitude of this noise is interpreted in terms of an avalanche gain produced by a multistep impact-ionization process involving both holes and electrons. The device structure imposes one positive and one negative feedback loop and exhibits a peak in the noise as a function of the drain voltage.

1f noise in GaAs MESFETS

Abstract An attempt was made to discriminate between number fluctuation and mobility fluctuation 1 f noise in GaAs MESFETs. It was found, that both models could explain the data, even though the mobility fluctuation 1 f model seems more likely.