Dmitri Mihhailov

Implementation in FPGA of Address-Based Data Sorting

The paper describes the hardware implementation and optimization of sorting algorithms that use data items as memory addresses with one-bit flags indicating presence of data. The proposed technique enables such type of address-based sorting to be applied either directly or through tree-walk tables permitting number of bits in sorted data items to be increased by constructing and traversing N-ary trees (N>2) composed of so called no-match and working nodes. The latter are organized in well balanced sub-trees of equal depth. It is allowed more than one data item to be assigned to leaves of working sub-trees and such sets of items are processed by fast acceleration circuits. Experiments and comparisons demonstrate that the proposed technique can be used efficiently in low cost FPGAs.

Parallel FPGA-Based Implementation of Recursive Sorting Algorithms

The paper describes the hardware implementation and optimization of parallel recursive algorithms that sort data using binary trees. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model of a hierarchical finite state machine (HFSM). Parallel processing is achieved by constructing N binary trees (N>1) and applying concurrent sorting to N trees at the same time with the aid of N communicating HFSMs. The paper presents new results in: 1) parallel sorting algorithms, 2) FPGA-based parallel architectures, and 3) the analysis and comparison of alternative and competitive techniques for implementing parallel recursive algorithms. Experiments demonstrate that the performance of sorting operations is increased compared to previous implementations.

Hardware implementation of recursive algorithms

The paper presents new results in the hardware implementation and optimization of recursive sequential and parallel algorithms using the known and a new model of a hierarchical finite state machine. Applicability and advantages of the proposed methods are confirmed through numerous examples of the designed hardware circuits that have been analyzed and compared. The results of experiments and FPGA-based prototyping demonstrate clearly that the proposed innovations enable the required hardware resources to be decreased achieving at the same time better performance of recursive sorting algorithms compared to known implementations both in hardware and in software.

Implementation of address-based data sorting on different FPGA platforms

Among numerous tasks that need to be solved, sorting is considered to be one of the most important. Since it is time consuming for large volumes of data, acceleration is greatly required for many practical applications. It is also important to discover such methods that take advantage of the implementation platform (due to its uniqueness) and consider not only the number of the required operations, but also efficiency of their implementation in hardware circuits. This paper evaluates implementations of address-based data sorting algorithms in field-programmable gate array (FPGA) circuits. It is demonstrated that the proposed technique can be used efficiently both in low cost FPGAs as well as in advanced FPGAs, and the number of sorted items (with sizes of up to 32 bits) can reach 232.

Application-specific hardware accelerator for implementing recursive sorting algorithms

The paper is dedicated to hardware accelerators for data sorting using tree-based recursive algorithms. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model of a hierarchical finite state machine. The paper presents new results in: 1) computational models and hardware architectures; 2) optimization and parallel execution of recursive sorting algorithms; 3) the analysis and comparison of alternative and competitive techniques for implementation of recursive sorting algorithms both in hardware and software. Experiments with the proposed FPGA-based hardware accelerators demonstrate that the performance of sorting operations is increased compared to known implementations.

Implementation of sorting algorithms in reconfigurable hardware

The paper discusses data sorting algorithms which create and traverse tree-like data structures and permit fast resorting. Optimization is achieved through rational grouping of previously developed methods allowing address-based representation and compact coding of data items. The results of hardware implementation of the algorithms and prototyping in FPGA (Field-Programmable Gate Arrays) demonstrate that: 1) sorting algorithms can be implemented efficiently in low-cost FPGA; 2) the developed coding technique permits data items to be compactly represented in memory; 3) combining different sorting methods produces the best results in terms of performance and memory requirements; 4) low-cost devices can only be used to tackle limited sets of data (up to 220 in a Spartan-3 1200 FPGA) and for processing more data either a more powerful FPGA or an external memory is required.

High-performance hardware accelerators for sorting and managing priorities

The paper describes the hardware implementation and optimization of algorithms that process tree-like data structures which are needed for numerous practical applications in such areas as databases, embedded systems, and networks requiring priority management. The emphasis is done on applications that involve fast processing of new incoming data items, such as resorting. Parallelism is achieved by constructing N binary trees (N>1) and applying concurrent operations to N trees at the same time with the aid of N communicating processing modules. It is shown that the considered technique can efficiently be combined with sorting networks, which gives new potentialities for optimization. Modeling in software, experiments with FPGA-based circuits on different computing platforms, and comparisons with the other known methods demonstrate that the performance is increased significantly. It is also shown that the proposed algorithms are easily scalable.

Optimization of FPGA-based circuits for recursive data sorting

The paper describes sequential and parallel methods of recursive data sorting that are applied to binary trees. Hardware circuits implementing these methods are based on the model of a hierarchical finite state machine, which provides support for recursion in hardware. It is shown that the considered technique allows the known optimization methods for conventional state machines to be applied directly. The described circuits have been implemented in commercial FPGAs and tested in numerous examples. Analysis and comparison of alternative and competitive techniques is also done in the paper.

Hardware implementation of recursive sorting algorithms

The paper describes methods of data sorting in hardware using parallel recursive algorithms over a binary tree. The implementation is based on communicating hierarchical finite state machines interacting with dedicated memories. Distinctive features of the proposed methods are balancing the tree to increase the performance of hardware implementation and the use of sorting networks combined with operations over the tree. Parallel processing is achieved through constructing and traversing different branches of the tree at the same time. The results of prototyping in FPGA and experiments demonstrate applicability and effectiveness of the proposed technique.

Multilevel models for data processing

The paper suggests multilevel models for data processing and demonstrates advantages of such models on examples of data sorting. Three different techniques are discussed, namely graph walk, using tree-like structures and sorting networks. The relevant implementations were done on the basis of hierarchical finite state machines and verified in commercially available FPGAs. Experiments and comparisons demonstrate that the results enable the performance of processing for different types of data to be increased compared to known implementations.