Dmitri Osintsev

Physical modeling of hot-carrier degradation for short- and long-channel MOSFETs

We present the first physics-based model for hot-carrier degradation which is able to capture degradation in both short- and long-channel SiON nMOSFETs. Degradation is considered to be due to the breaking of Si-H bonds at the SiON/Si interface. Contrary to previous modeling attempts, our approach now correctly considers the intricate superposition of multivibrational bond excitation and bond rupture induced by a solitary hot carrier based on experimentally confirmed distributed activation energies. All processes are treated as competing pathways, leading to bond dissociation from all vibrational levels. These rates are determined by the carrier acceleration integral and by the bond energetics. The acceleration integral is calculated using the carrier energy distribution. Corresponding distribution functions are found by a thorough solution of the Boltzmann transport equation. We demonstrate that electron-electron scattering plays the dominant role. As for the bond energetics, we consider the dispersion of the activation energy as well as its reduction induced by the interaction of the bond dipole moment with the electric field. All the model ingredients are incorporated into the same simulation framework based on the deterministic solver of the Boltzmann transport equation, ViennaSHE.

A predictive physical model for hot-carrier degradation in ultra-scaled MOSFETs

We present and validate a novel physics-based model for hot-carrier degradation. The model incorporates such essential ingredients as a superposition of the multivibrational bond dissociation process and single-carrier mechanism, dispersion of the bond-breakage energy, interaction of the electric field and the dipole moment of the bond, and electron-electron scattering. The main requirement is that the model has to be able to cover HCD observed in a family of MOSFETs of identical architecture but with different gate lengths under diverse stress conditions using a unique set of parameters.

Switching time and current reduction using a composite free layer in magnetic tunnel junctions

The theoretical predictions [1] and the experiments [2] of spin transfer switching demonstrated that the spin transfer torque random access memory (STTRAM) is one of the promising candidates for future universal memory. The basic element of the STTRAM is a magnetic tunnel junction (MTJ), a sandwich of two magnetic layers separated by a thin non-magnetic spacer (Fig.1a). The reduction of the current density required for switching and the increase of the switching speed are the most important challenges in STTRAM research [3]. It has been demonstrated [4] that the critical current density is decreased in a penta-layer magnetic tunnel junction as shown in Fig.1b.

Properties of Silicon Ballistic Spin Fin-Based Field-Effect Transistors

We investigate the properties of ballistic fin-structured silicon spin field-effect transistors. The spin transistor suggested first by Datta and Das employs spin-orbit coupling to introduce the current modulation. The major contribution to the spin-orbit interaction in silicon films is of the Dresselhaus type due to the interface-induced inversion symmetry breaking. The subband structure in silicon confined systems is obtained with help of a two-band k·p model and is in good agreement with recent density functional calculations. It is demonstrated that fins with [100] orientation display a stronger modulation of the conductance as function of spin-orbit interaction and magnetic field and are thus preferred for practical realizations of silicon SpinFETs.

(Late) Essential ingredients for modeling of hot-carrier degradation in ultra-scaled MOSFETs

We present a novel approach to hot-carrier degradation (HCD) simulation, which for the first time considers and incorporates mechanisms crucial for HCD. First, two main pathways of Si-H bond dissociation, namely bond-breakage triggered by a single hot carrier and induced by multivibrational bond excitation, are combined and considered consistently. Second, we show how drastically electron-electron scattering affects the whole HCD picture. Furthermore, dispersion of the activation energy of bond dissociation substantially changes defect generation rates. Finally, the interaction between the electric field and the dipole moment of the bond leads to interface states created near the source end of the channel. To demonstrate the importance of all these peculiarities we use ultra-scaled n-MOSFETs with a channel gate of 65 nm.

Transport properties of spin field-effect transistors built on Si and InAs

We investigate the properties of ballistic spin field-effect transistors (SpinFETs). First we show that the amplitude of the tunneling magnetoresistance oscillations decreases dramatically with increasing temperature in SpinFETs with the semiconductor channel made of InAs. We also demonstrate that the [100] orientation of the silicon fin is preferred for practical realizations of silicon SpinFETs due to stronger modulation of the conductance as a function of spin-orbit interaction and magnetic field.

Using strain to increase the reliability of scaled spin MOSFETs

We investigate the surface roughness induced spin relaxation in scaled spin MOSFETs. We show that the spin-flip hot spots characterized by strong spin relaxation appear in thin MOSFET channel. Strain can efficiently move these hot spots outside of the states occupied by carriers, resulting in a substantial increase of the spin lifetime.

Strain-induced reduction of surface roughness dominated spin relaxation in MOSFETs

Semiconductor spintronics is a rapidly developing field with large impact on microelectronics. Using spin may help to reduce power consumption and increase computational speed. Silicon is perfectly suited for spin-based applications. It is characterized by a weak spin-orbit interaction which should result in a long spin lifetime. However, recent experiments indicate the lifetime is greatly reduced in gated structures. Thus, understanding the peculiarities of the spin-orbit effects on the subband structure and details of the spin propagation in surface layers and thin silicon films is urgently needed. We investigate the contribution of the spin-orbit interaction to the equivalent valley splitting and calculate the spin relaxation matrix elements by using a perturbative k ⋅p approach. We demonstrate that applying uniaxial stress along the [110] direction may considerably suppress electron spin relaxation in silicon surface layers and thin films.

Silicon-on-insulator for spintronic applications: spin lifetime and electric spin manipulation

Abstract With complementary metal-oxide semiconductor feature size rapidly approaching ultimate scaling limits, the electron spin attracts much attention as an alternative to the electron charge degree of freedom for low-power reprogrammable logic and nonvolatile memory applications. Silicon, the main element of microelectronics, appears to be the perfect material for spin-driven applications. Despite an impressive progress in understanding spin properties in metal-oxide-semiconductor field-effect transistors (MOSFETs), spin manipulation in a silicon channel by means of the electric field–dependent Rashba-like spin–orbit interaction requires channels much longer than 20 nm channel length of modern MOSFETs. Although a successful realization of the spin field-effect transistor seems to be unlikely without a new concept for an efficient way of spin manipulation in silicon by purely electrical means, it is demonstrated that shear strain dramatically reduces the spin relaxation, thus boosting the spin lifetime by an order of magnitude. Spin lifetime enhancement is achieved by lifting the degeneracy between the otherwise equivalent unprimedsubbands by [110] uniaxial stress. The spin lifetime in stressed ultra-thin body silicon-on-insulator structures can reach values close to those in bulk silicon. Therefore, stressed silicon-on-insulator structures have a potential for spin interconnects.

Modeling of spin-based silicon technology

Electron spin attracts much attention as an alternative degree of freedom for low-power reprogrammable logic and non-volatile memory applications. Silicon appears to be the perfect material for spin-driven applications. Recent progress and challenges in simulating spin-based devices are briefly reviewed. Strain-induced enhancement of the electron spin lifetime in silicon thin films is predicted and its impact on spin transport in SpinFETs is discussed. A new design of the spin-based nonvolatile memory cell, MRAM, is presented. By means of micromagnetic simulations it is demonstrated that the new design leads to a reduction of the switching time of the cell. Any two memory cells from a MRAM array can form an implication logic gate. It is shown how by using these gates an intrinsic non-volatile logic-in-memory architecture is realized.