Dmitry Korchemny

Deterministic dynamic monitors for linear-time assertions

We describe a framework for dynamic verification of temporal assertions based on assertion compilation into deterministic automata. The novelty of our approach is that it allows efficient dynamic verification of general linear temporal formulas written in formal property specification languages such as LTL, ForSpec, PSL, and SVA, while the existing approaches are applicable to limited subsets only. We also show an advantage of the described framework over industrial simulators, which typically use transaction-based verification. Another advantage of our approach is its ability to use deterministic checkers directly for hardware emulation. Finally, we compare the deterministic compilation with the OBDD-based on-the-fly simulation of deterministic automata. We show that although the OBDD-based simulation method is much slower, the two methods may be efficiently combined for hybrid simulation, when the RTL signals in assertions are mixed with symbolic variables.

Efficient LTL compilation for SAT-based model checking

This work describes an algorithm of automata construction for LTL safety properties, suitable for bounded model checking. Existing automata construction methods are tailored to BDD-based symbolic model checking. The novelty of our approach is that we construct deterministic automata, unlike the standard approach, which constructs nondeterministic automata. We show that the proposed method has significant advantages for bounded model checking over traditional methods.

SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience

This paper provides insight into the development of System Verilog Assertions standardization efforts. Specifically it covers the evolution from Accellera 3.1a version to its current state of standardization (the upcoming SVA2012 release). Insight into the new features, changes and the reasons for the same exposes users of SVA to the direction the standard is evolving.

Introduction to Assertion Based Formal Verification

In this and the following chapter, we probe deeper into the principles of formal assertion-based verification: its methods of application, formal semantics of assertions, and underlying models and algorithms. In this chapter our objective is to familiarize the reader with the terminology as well as the methodologies that have proven to be indispensable for many design groups.

SystemVerilog Language Overview

This chapter introduces some important SystemVerilog features that are often needed for writing assertions, or used in conjunction with assertions to support other tasks.

An Apology for Local Variables

This chapter gives an intuitive introduction to SystemVerilog Assertion local variables based on examples. Local variables are a powerful feature of SVA that enable an assertion to capture the value of an expression at a specified point in its evaluation and store that value for later reference or modification. While local variables do not increase the theoretical expressive power of SVA, they do make the encoding of many assertions much easier, and they help to avoid the need to create auxiliary state machines to support assertions.

Let, Sequence and Property Declarations; Inference

In SystemVerilog, modules, programs, interfaces, checkers, functions, and tasks provide means for reuse, and for abstracting and hiding details. SystemVerilog assertions provide such means too. This is achieved using parameterized let, sequence, and property declarations. Their argument lists as well as instantiation semantics are quite different from the other reuse features. In addition, certain kinds of actual arguments can be inferred from the instantiation context. Similar to sequences and properties, let declarations allow to abstract expressions, making code more readable and reusable. let can be used anywhere, not only in assertions. One of their intended uses is for defining reusable parameterizable expressions for immediate and deferred assertions.

Using computational biology methods to improve post-silicon microprocessor testing

Hardware testing is an expensive process at different stages of hardware design and manufacturing. It includes pre-silicon, post-silicon and production testing. Testing is expensive both in terms of manpower and in computing resources, and it directly affects the hardware profitability and the time to market. This problem is especially acute for Systems on Chip (SoC) where both manpower and timing constraints are very tight. Therefore it is important to reduce the total number of tests without sacrificing testing quality. To learn the behavior of a large test set smart algorithms are needed. In addition, visualization techniques can provide a birds-eye view of the total test coverage data. Our goal is to optimize post-silicon hardware test suites based on coverage metrics and to provide test coverage visualization. We utilize ideas and methods developed in machine learning and bioinformatics, and develop new biology-inspired methods to analyze and visualize post-silicon data. In a different effort, we are exploring combinatorial methods of covering and domination for the same problem. Mathematically, the results of post-silicon tests can be presented as a matrix whose rows correspond to the tests performed on the chip and columns correspond to certain events of interest occurring during the tests runs. The matrix values are the number of times the event occurred in the test. Such a matrix can then be used to define a similarity measure between tests and analyze their relations. In computational biology (bioinformatics), advanced methods were developed to handle gene expression microarray data [1], which has a similar structure. The result of a set of microarray experiments is a gene expression values matrix where rows are genes and columns are conditions. A rich spectrum of methods was developed for analysis of such data [2], and we adapt them for the post-silicon analysis. For example, clustering techniques divide the tests into similarity groups, identifying subsets of tests that cover similar events. The identified groups can then be analyzed by the hardware validation engineers in order to identify coverage holes and to improve the test suite quality. In addition, similar test groups can be investigated for enrichment of certain chip properties as done for gene groups with biological properties. This can give further insight on the chips operation and the tests scope. Gene expression software tools that combine advanced analysis and visualization can assist in visual comprehension of the post silicon validation process. We are using for this task the Expander tool developed in Prof. Shamirs group [3-5]. We describe initial results obtained by applying computational biology methods to post-Si test suite optimization and visualization. Though we experimented only with post-silicon test data, most of the developed methods should be applicable with appropriate modifications also to pre-silicon, production, and even to software testing.

SystemVerilog Language and Simulation Semantics Overview

SystemVerilog language evolved from Verilog with three main goals: 1. To add features for describing test benches such that the stimulus generation portion of verification can go hand in hand with the design portion, replacing troublesome ad-hoc means for generating stimuli. Testbenches are often written using Verification Programming Interface(VPI) [7] to connect to external means such as verification languages, C/C + + programs [53], and scripts. 2. To add features for checking the expected behavior in simulation and formal methods. These features are related to assertions. 3. To simplify expressing hardware designs by providing language constructs such as struct typedef, and new variants of always procedure.

Debugging Assertions and Efficiency Considerations

Properties and sequences allow us to describe complex behaviors in a very compact declarative form. That form is quite different from the procedural style used for writing RTL and other design models as well as test benches. Thus, assertions may also need a different style for debugging them. Issues related to the run time and memory overheads for complex temporal assertions also need to be addressed. The same behavior may be expressed using different assertions. Each may have different efficiency in formal verification and simulation. We discuss both debugging and efficiency in this chapter.