Eduard Cerny

Variable ordering on multiway decision graphs

The paper presents variable (re)ordering methods for Multiway Decision Graphs (MDG). MDGs have proved to be a powerful tool for automated hardware verification of RTL designs. To reduce the effects of the state explosion problem, we explore automatic static and dynamic variable ordering algorithms for MDG. Compared with ROBDDs, the situation is complicated by the presence of first order terms in MDGs. The static variable ordering algorithm is based on several heuristic rules, and the dynamic reordering algorithm that minimizes the size of the MDGs during the verification process combines the merits of symmetry and state group sifting. Experimental results on benchmarks show the effectiveness of our method.

Synthesis of checker EFSMs from timing diagram specifications

Efficient design verification is a major preoccupation in hardware systems design. We report on a method that assists the verification of the implementations of synchronous bus protocols (e.g., PCI). To this end we convert a timing diagram specification of the protocol in the form of hierarchical annotated action diagrams (HAAD) into synchronous state machines-checkers that can be used to observe the activity on the bus during simulation, emulation or formal verification and signal an error signal if a protocol violation is detected. The checkers are coded in synthesizable RT-level Verilog or VHDL. We illustrate the method on a subset of the PCI bus protocol.

Introduction to Assertion Based Formal Verification

In this and the following chapter, we probe deeper into the principles of formal assertion-based verification: its methods of application, formal semantics of assertions, and underlying models and algorithms. In this chapter our objective is to familiarize the reader with the terminology as well as the methodologies that have proven to be indispensable for many design groups.

SystemVerilog Language Overview

This chapter introduces some important SystemVerilog features that are often needed for writing assertions, or used in conjunction with assertions to support other tasks.

An Apology for Local Variables

This chapter gives an intuitive introduction to SystemVerilog Assertion local variables based on examples. Local variables are a powerful feature of SVA that enable an assertion to capture the value of an expression at a specified point in its evaluation and store that value for later reference or modification. While local variables do not increase the theoretical expressive power of SVA, they do make the encoding of many assertions much easier, and they help to avoid the need to create auxiliary state machines to support assertions.

Let, Sequence and Property Declarations; Inference

In SystemVerilog, modules, programs, interfaces, checkers, functions, and tasks provide means for reuse, and for abstracting and hiding details. SystemVerilog assertions provide such means too. This is achieved using parameterized let, sequence, and property declarations. Their argument lists as well as instantiation semantics are quite different from the other reuse features. In addition, certain kinds of actual arguments can be inferred from the instantiation context. Similar to sequences and properties, let declarations allow to abstract expressions, making code more readable and reusable. let can be used anywhere, not only in assertions. One of their intended uses is for defining reusable parameterizable expressions for immediate and deferred assertions.

SystemVerilog Language and Simulation Semantics Overview

SystemVerilog language evolved from Verilog with three main goals: 1. To add features for describing test benches such that the stimulus generation portion of verification can go hand in hand with the design portion, replacing troublesome ad-hoc means for generating stimuli. Testbenches are often written using Verification Programming Interface(VPI) [7] to connect to external means such as verification languages, C/C + + programs [53], and scripts. 2. To add features for checking the expected behavior in simulation and formal methods. These features are related to assertions. 3. To simplify expressing hardware designs by providing language constructs such as struct typedef, and new variants of always procedure.

Debugging Assertions and Efficiency Considerations

Properties and sequences allow us to describe complex behaviors in a very compact declarative form. That form is quite different from the procedural style used for writing RTL and other design models as well as test benches. Thus, assertions may also need a different style for debugging them. Issues related to the run time and memory overheads for complex temporal assertions also need to be addressed. The same behavior may be expressed using different assertions. Each may have different efficiency in formal verification and simulation. We discuss both debugging and efficiency in this chapter.

Formal Verification and Models

In this chapter we introduce basic notions of formal verification: the formal verification model and the system clock. We define important classes of properties – safety and liveness – and discuss how formal verification efficiency depends on the property class. We provide an alternative property classification into strong and weak depending on the requirements imposed on the property clock. To illustrate the concept of strong operators, we discuss several advanced strong SVA operators. We conclude this chapter with the description how immediate, deferred, and embedded concurrent assertions are treated in formal verification. This chapter does not require any preliminary knowledge except for the familiarity with Boolean logic. We also assume that the reader is familiar with the notion of a set, and with the basic operations on sets, like union, intersection, and complement. Other mathematical notions used in this chapter, such as relations, quantifiers, automata, and languages, are briefly explained in the text as needed.

Assertion System Functions and Tasks

In this chapter we describe two groups of assertion system functions: system functions analyzing and counting bits in a bit vector, and sampled value functions—system functions returning past, present, and future sampled values of integral expressions. We also discuss usage of the system (or global) clock in assertions, mostly in the context of global clocking sampled value functions. We conclude the chapter by explaining tasks that allow controlling assertion evaluation and the execution of action blocks.