Dmitry Zinoviev

RSFQ TECHNOLOGY: PHYSICS AND DEVICES

Rapid Single-Flux-Quantum (RSFQ) logic, based on the representation of digital bits by single quanta of magnetic flux in superconducting loops, may combine several-hundred-GHz speed with extremely low power dissipation (close to 10-18 Joule/bit) and very simple fabrication technology. The drawbacks of this technology include the necessity of deep (liquid-helium-level) cooling of RSFQ circuits and the rudimentary level of the currently available fabrication and testing facilities. The objective of this paper is to review RSFQ device physics and also discuss in brief the prospects of future development of this technology in the light of the tradeoff between its advantages and handicaps.

FLUX chip: design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-/spl mu/m LTS technology

We describe the design and implementation of a single-chip microprocessor based on LTS Rapid Single-Flux-Quantum (RSFQ) technology. Two such chips are to be used in a dual-processor module, being developed by a SUNY-TRW collaboration as a spin-off of the HTMT project. Each FLUX chip represents a simple 16-bit 2-way long-instruction-word (LIW) microprocessor with a pipelined instruction memory of 30-bit instructions, decode and issue units, 8 integer ALUs interlaced with 8 registers, and input/output ports through which two FLUX chips can communicate with each other at a 7-GHz communication rate over a multi-layer MCM. The FLUX instruction set consists of /spl sim/25 instructions. High performance is reached with a scalable design featuring (1) a very high clock rate, (2) localized, regular and ultrapipelined processing in registers with very short wires, (3) instruction-level parallelism utilization with bit-level resolution of data hazards. A 16-bit implementation of FLUX processor consists of /spl sim/90,000 Josephson junctions on a /spl sim/10 mm/spl times/15 mm chip area. Our estimates show that the processor will be able to operate at clock frequencies up to 20 GHz when implemented using TRWs 4 kA/cm/sup 2/, 1.75-/spl mu/m Nb-trilayer technology.

Octopux: an advanced automated setup for testing superconductor circuits

An integrated multipurpose setup for the automated testing of superconductor devices and circuits has been designed, implemented, and installed in the RSFQ Laboratory of the State University of New York at Stony Brook. The extendable and modular design of the setup allows a wide variety of low-frequency superconductor experiments to be carried out including those that require immediate interaction between the setup and the researcher.

COOL-0: Design of an RSFQ subsystem for petaflops computing

We discuss a preliminary design of a Rapid Single-Flux-Quantum (RSFQ) subsystem for general-purpose computers with petaflops-scale performance. The subsystem is being developed at Stony Brook within the framework of the Hybrid Technology MultiThreading (HTMT) project. COOL-0 design is based on 0.8-/spl mu/m RSFQ technology which enables the implementation of superconductor processing elements (SPELLs) operating at clock frequencies up to 100 GHz pipelined cryo-memory (CRAM) with 30 ps cycle time and interprocessor network (CNET) with a bandwidth of 30 Gbps per channel. The main architectural challenge is an almost 1,000-fold speed difference between the RSFQ processors and room-temperature SRAM comprising the second level of the HTMT memory hierarchy. The proposed solution to the problem is hardware support for two-level multithreading and block transfer techniques in SPELLs. Our preliminary estimates show that an RSFQ subsystem with 4 K SPELLs and a 4-Gbyte CRAM may be sufficient to achieve the performance close to 0.5 petaflops for computationally intensive program kernels. COOL-0 would occupy a physical space of about 0.5 m/sup 3/ and dissipate power as low as 250 Watts (at helium temperature). These numbers present a dramatic improvement compared to a hypothetical purely-semiconductor petaflops-scale computer.

Feasibility study of RSFQ-based self-routing nonblocking digital switches

This paper describes the results of a preliminary analysis of ultra-fast low-power superconductor digital switches based on Rapid Single-Flux-Quantum (RSFQ) technology. In particular, RSFQ-based crossbar, Batcher-banyan, and shared bus switching cores have been considered, and the possible parameters of these circuits have been estimated. The results show that the proposed RSFQ digital switches with overall throughput of 7.5 Tbps operating at an internal clock frequency of /spl sim/60 GHz and dissipating very little power could effectively compete with their semiconductor and photonic counterparts.

Experimental characterization of bit error rate and pulse jitter in RSFQ circuits

Rapid Single Flux Quantum (RSFQ) logic is well-known for its ultra-high switching speed and extremely low power consumption. In this paper, we present two original experiments to demonstrate that its also a reliable technology and its reliability is sufficient even for such a large-scale system as a proposed petaflops-scale HTMT computer. We have measured the bit error rate (BER) for a circular register of inverters representing a critical path of a 64-bit integer adder, and timing jitter in a 200 Josephson junction (JJ) long transmission line, imitating a branch of a clock distribution tree, both being important and representative building blocks of the HTMT computer. For the adder critical path we have demonstrated the highest clock frequency of 17 GHz, latency of 860 ps and BER of 10/sup -19/ for 3.5 /spl mu/m technology of HYPRES, Inc. The value of timing jitter was 200 fs per JJ for 1.5 /spl mu/m technology of TRW, Inc. These figures are in good agreement with our simulations.

Design and implementation of an RSFQ switching node for petaflops networks

This work is part of a project to design a petaflops-scale computer using a hybrid technology multi-threaded architecture (HTMT). A high-bandwidth low-latency switching network (CNET) based on RSFQ logic/memory family comprises the core of the superconductor part of the HTMT system, interconnecting 4,096 processors. We present a preliminary low-level design and partial experimental implementation of a multi-credit RSFQ network switching node with the estimated throughput of 7/spl middot/10/sup 10/ 85-bit-parallel packets per second, service latency of 109 ps, and dissipated power of 4.6 mW.

Application of credit-based flow control to RSFQ micropipelines

Traditional micropipelines based on handshaking mechanisms are simple and reliable, but their throughput is limited by the round-trip flight time between two consecutive micropipeline stages. We propose an RSFQ implementation of a micropipeline with simple credit-based flow control that can hide the round-trip latency and significantly improve the throughput. In this paper, we present numerically calculated and experimentally measured throughput for several types of RSFQ credit-controlled micropipelines (including the special case of a micropipeline with only one credit), and their critical comparison.

COOL-1: the next step in RSFQ computer design

Abstract Recent progress in the design of a superconductor digital system for high-performance computing, based on the RSFQ logic family, is briefly outlined.

Rapid single-flux quantum fast-packet switching element

We present the design of a rapid single-flux quantum N X N fast-packet TDM switching element that can be used in ATM packet switches. Using simple 3.5-micrometers niobium-trilayer technology, this device would allow the external exchange rate fe equals 10 Gb/sec per switched channel at the internal clock frequency f0 equals 40 GHz. The element structure implies that a separate unit provides the address of the destination channel for each packet and resolves packet contentions.