Konstantin K. Likharev

RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems

Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output latch (register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology.<<ETX>>

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 1014 synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current–voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices

This paper describes a digital logic architecture for ‘CMOL’ hybrid circuits which combine a semiconductor–transistor (CMOS) stack and two levels of parallel nanowires, with molecular-scale nanodevices formed between the nanowires at every crosspoint. This cell-based, field-programmable gate array (FPGA)-like architecture is based on a uniform, reconfigurable CMOL fabric, with four-transistor CMOS cells and two-terminal nanodevices (‘latching switches’). The switches play two roles: they provide diode-like I –V curves for logic circuit operation, and allow circuit mapping on CMOL fabric and its reconfiguration around defective nanodevices. Monte Carlo simulations of two simple circuits (a 32-bit integer adder and a 64-bit full crossbar switch) have shown that the reconfiguration allows one to increase the circuit yield above 99% at the fraction of bad nanodevices above 20%. Estimates have shown that at the same time the circuits may have extremely high density (approximately 500 times higher than that of the usual CMOS FPGAs with the same design rules), while operating at higher speed at acceptable power consumption. (Some figures in this article are in colour only in the electronic version)

Layered tunnel barriers for nonvolatile memory devices

Fowler–Nordheim tunneling of electrons through “crested” energy barriers (with the height peak in the middle) is much more sensitive to applied voltage than that through barriers of uniform height. Calculations for trilayer barriers, with layer parameters typical for wide-band-gap semiconductors, have shown that by merely doubling the voltage, the tunnel current may be changed by more than 16 orders of magnitude. It is argued that this effect may be used for the implementation of nonvolatile random-access memories combining a few ns cycle time with a few years retention time and for ultradense electrostatic data storage.

Single‐electron transistor logic

We present the results of numerical simulations of a functionally complete set of complementary logic circuits based on capacitively coupled single‐electron transistors (CSETs). The family includes an inverter/buffer stage, as well as two‐input NOR, NAND, and XOR gates, all using similar tunnel junctions, and the same dc bias voltage and logic levels. Maximum operation temperature, switching speed, power consumption, noise tolerances, error rate, and critical parameter margins of the basic gates have been estimated. When combined with the data from a preliminary geometrical analysis, the results indicate that implementation of the CSET logic family for operation at T∼20 K will require fabrication of structures with ∼2‐nm‐wide islands separated by ∼1‐nm‐wide tunnel gaps.

Mutual phase-locking in Josephson junction arrays

Abstract We discuss mutual phase locking of Josephson oscillations in an array of Josephson junctions. The discussion is focussed on phase locking due to electromagnetic coupling. The theoretical analysis is based on a secular-term free perturbative solution of the resistively shunted junction model. Detailed experimental results on phase locking of two coupled micro-bridges are presented. The perturbation analysis provides a complete qualitative description of the experimental results, including the effects of fluctuations on phase locking and the oscillation linewidth. Measurements have also been made on linear arrays of up to 100 junctions. The observed increase in the radiated power (as N2) and the decrease in the radiation linewidth (as N−1) are all in agreement with the theory. Optimized arrays suitable for use as either microwave and millimeter wave radiation sources or as mixers are discussed. The properties of the arrays are found to solve various problems associated with the use of single junctions as mixers, such as excess noise temperature, limited dynamic range and low sensitivity for narrow band signals.

Rapid single flux quantum T-flip flop operating up to 770 GHz

Rapid Single Flux Quantum (RSFQ) T-flip flops (TFFs) operating up to 770 GHz have been demonstrated at 4.2 K. The devices, consisting of either resistively shunted or unshunted Josephson junctions, are fabricated using a planarized Nb/AlO/sub x//Nb trilayer process. Electron beam lithography is used to pattern all levels with a minimum junction area less than 0.1 /spl mu/m/sup 2/. Critical current densities of 0.5 mA//spl mu/m/sup 2/ and 2.5 mA//spl mu/m/sup 2/ are used for the shunted (tested at 1.8 K) and unshunted devices (tested at 4.2 K) respectively. The input and output frequencies of the TFFs are obtained from the input and output voltages by the Josephson relation. The output voltage is exactly half of the input voltage when the divide-by-two operation is correct.

Prospects for terabit-scale nanoelectronic memories

We have calculated the minimu mc hip are aoverhead, and hence the bit density reduction, that may be achieved by memory array reconfiguration (bad bit exclusion), combined with error correction code techniques, in prospective terabit-scale hybrid semiconductor/nanodevice memories, as a function of the nanodevice fabrication yield and the micro-to-nano pitch ratio. The results show that by using the best (but hardly practicable) reconfiguration and block size optimization, hybrid memories with a pitch ratio of 10 may overcome purely semiconductor memories in useful bit density if the fraction of bad nanodevices is below ∼15%, while in order to get an order-of-magnitude advantage in density, the number of bad devices has to be decreased to ∼2%. For the simple ‘Repair Most’ technique of bad bit exclusion, complemented with the Hamming-code error correction, these numbers are close to 2% and 0.1%, respectively. When applied to purely semiconductor memories, the same technique allows us to reduce the chip area ‘swelling’ to just 40% at as many as 0.1% of bad devices. We have also estimated the power and speed of the hybrid memories and have found that, at ar easonable choice of nanodevice resistance, both the additional power an ds peed loss due to the nanodevice subsystem may be negligible. (Some figures in this article are in colour only in the electronic version)

CrossNets: High-Performance Neuromorphic Architectures for CMOL Circuits

Abstract: The exponential, Moores Law, progress of electronics may be continued beyond the 10‐nm frontier if the currently dominant CMOS technology is replaced by hybrid CMOL circuits combining a silicon MOSFET stack and a few layers of parallel nanowires connected by self‐assembled molecular electronic devices. Such hybrids promise unparalleled performance for advanced information processing, but require special architectures to compensate for specific features of the molecular devices, including low voltage gain and possible high fraction of faulty components. Neuromorphic networks with their defect tolerance seem the most natural way to address these problems. Such circuits may be trained to perform advanced information processing including (at least) effective pattern recognition and classification. We are developing a family of distributed crossbar network (CrossNet) architectures that permit the combination of high connectivity neuromorphic circuits with high component density. Preliminary estimates show that this approach may eventually allow us to place a cortex‐scale circuit with about 1010 neurons and about 1014 synapses on an approximately 10 × 10 cm2 silicon wafer. Such systems may provide an average cell‐to‐cell latency of about 20 nsec and, thus, perform information processing and system training (possibly including self‐evolution after initial training) at a speed that is approximately six orders of magnitude higher than in its biological prototype and at acceptable power dissipation.

Nanoscale field-effect transistors: An ultimate size analysis

We have used a simple, analytically solvable model to analyze the characteristics of dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with 10 nm-scale channel length L. The model assumes ballistic dynamics of two-dimensional electrons in an undoped channel between highly doped source and drain. When applied to silicon n-MOSFETs, calculations show that the voltage gain (necessary for logic applications) drops sharply at L∼10 nm, while the conductance modulation remains sufficient for memory applications until L∼4 nm.