Do Dormans

A Quantitative Study of Endurance Characteristics and Its Temperature Dependance of Embedded Flash Memories With 2T-FNFN nor Device Architecture

A quantitative study on the endurance of an embedded Flash memory with 2T-FNFN device architecture in a 0.13-mum technology node has been presented in this paper. Physical insights of 2T-FNFN device degradation have been obtained through stressing and characterizing large parallel arrays of flash transistors (with floating gate connected). Experiments are carried out on large random accessible arrays based on the 2T-FNFN cells, at a wide temperature range and with different program/erase (P/E) voltages. An empirical model has been developed to describe the temperature-dependent degradation of the program window. This model fits the experimental data over the whole temperature range, and the endurance performance with single-shot P/E cycles exceeds 1 million cycles. This paper provides a method for flash endurance characterization and modeling.

Characterization and modeling of program/erase induced device degradation in 2T-FNFN-NOR flash memories

In this paper, we report the program/erase degradation mechanisms in two transistor (2T) Fowler-Nordheim (FN) tunneling operated flash memories, based on extensive experimental study of the degradation characteristics of such 2T-FNFN test memory arrays and reference transistor arrays from several generation process technologies. A quantitative model has been established describing the degradation characteristics under various stress conditions (i.e. degradation due to program/erase cycling at various voltages and temperatures). A software tool has been developed to estimate the reliability performance of various products under different use conditions. This model (and tool) can also be used to estimate the product reliability performance in future process generations.

Experimental Study of Charge Displacement in Nitride Layer and its Effect on Threshold Voltage Instability of Advanced Flash Memory Devices

The effect of charge displacement in nitride layer of ONO stack in scaled flash cells are experimentally studied by using gate stress measurements. The redistribution of charge is found to follow Poole-Frenkel conduction mechanisms. However, the measurements on scaled devices show significant random telegraph noise. The noise will be even more pronounced in future scaled devices.

Junction Optimization for Embedded 40nm FN/FN Flash Memory

2-transistor (2T) cell technology used for embedded non-volatile memory (eNVM) has been scaled down to 40nm node. To enable aggressive cell scaling, the array architecture is modified compared to previous generations and the channel length of cell is drastically reduced requiring steep cell junctions, which give rise to new disturb phenomena. This paper describes how to safeguard the drain disturb immunity in 40nm 2T eNVM, while maintaining the intrinsic 2T robustness.

Embedded FLASH memory thermal budget impact on core CMOS 90nm devices

In an embedded FLASH 90 nm technology, core devices behavior is modified by the thermal budget needed to process the specific FLASH dielectrics. When these steps are performed after the logic poly deposition, we observe two main kinds of changes: first the substrate doping is modified due to diffusion and segregation effects. Then, the poly morphology changes, this leads to larger poly grain size and gate doping change. To limit these effects and maintain the full compatibility with CMOS logic, thermal budget limitations are finally presented.

Reduction of Bitline to Control Gate Leakage for Improved Embedded 0.18 um FLASH Yield and Reliability

In this paper we illustrate the modifications to the standard logic CMOS process flow that are necessary to control the bitline to control gate leakage in embedded 0.18 μm FLASH memory arrays. In particular, it will be shown that phase-shift masks for bitline patterning and dual-frequency boarderless nitride deposition are required to guarantee a reliable and manufacturable bitline to control gate isolation.

A simple and accurate method to extract neutral threshold voltage of floating gate flash devices and its application to flash reliability characterization

A commonly used method to determine the neutral threshold voltage (Vtn) of floating gate device is by measuring the Vt of the device after a UV erasure treatment. However, such a UV erasure treatment is no more feasible for advanced technologies with Cu backend, because of limited UV transparency of the dielectric stack. A fully electrical method is needed for the determination of such a Vtn. Based on the Fowler-Nordheim (FN) tunneling formula, and by measuring the FN programming and erasure speed characteristics, a perfect straight line can be obtained if I/Eox versus ln(t) is plotted. From the fitting parameters of such a straight line, the Vtn value can be obtained. This method, that is based on the physics of FN tunneling, has been used to derive the neutral threshold voltage (Vtn) of the 90 nm 2T-FNFN embedded flash device before and after P/E cycling. The results give us a good insight in device degradation speed.

Bake enhanced erratic behavior in gate stress characteristics in flash memories

Bake enhanced degradation of gate disturbance of flash cells has been studied. It is found that the worst-case situation exists when the cells are baked in the erased state. The number of cells appearing in the tail distribution can be three times as high when the cells are baked in the erased state than those cells baked in the programmed state. This bake state dependent gate stress behavior can be related to process induced mobile ions or to positive centers in the tunnel oxide.