A. Cacciato

Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4F2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.

Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology

The hybrid floating gate (FG) concept, previously demonstrated in FG capacitors, has been proven in fully integrated stacked memory cells. Results not only confirm the high potential of the concept in terms of improved program performance, but also show excellent data retention and program/erase cycling endurance. Key for achieving this result has been the optimization of the sidewall and spacer processing. Hybrid FG cells are therefore a viable solution to extend the nand Flash memory roadmap below the 20-nm technology node.

Nitride Engineering for Improved Erase Performance and Retention of TANOS NAND Flash Memory

TANOS charge trap flash (CTF) with Al₂O₃-Si₃N₄-SiO₂ memory stack and TaN metal gate is a candidate technology to replace conventional floating gate technology for multi-level NAND applications beyond the 32nm node. The main drawbacks of TANOS to date are poor erase performance (in terms of speed and/or saturated level) as well as insufficient retention in the highest programmed state.

Novel dual layer floating gate structure as enabler of fully planar flash memory

Flash pitch scaling will lead to cells for which the wordline no longer fits between the floating gates, which results in loss of sidewall coupling, causing unacceptable program saturation due to IPD leakage. We present a dual layer poly/metal floating gate (FG) memory device avoiding this saturation and demonstrate +4V programming above the fresh level in a fully planar cell without sidewall coupling using an Al2O3 IPD. The data retention at 200C and cycling performance up to 100k cycles are similar to cells with poly FG.

Investigation of Window Instability in Program/Erase Cycling of TANOS NAND Flash Memory

TANOS endurance is mainly governed by interface traps at the substrate-tunnel oxide interface, generated upon electrical stress, rather than by fixed charge in the tunnel oxide/blocking dielectric or by incomplete charge compensation in the nitride. As a result of acceptor resp. donor trap formation in the upper resp. lower half of the Si band gap, the V,h program/erase window monotonically shifts upward whereas the V fb window exhibits turn-around behavior. Interface trap generation rate is highest during the erase operation and depends also on the memory stack process.

Physical Understanding of SANOS Disturbs and VARIOT Engineered Barrier as a Solution

Both read and program disturb sensitivity are identified to be major drawbacks for nitride-based NAND Flash arrays. The crucial aspects to understand the disturbs are the injection of electrons at low fields through the bottom oxide, and the tunneling through the top oxide during programming. These results are exploited to identify possible improvements of the device. A VARIOT engineered barrier is proposed to replace the bottom oxide layer in order to significantly reduce the disturb problem.

A Consistent Model for the SANOS Programming Operation

An accurate model for the SANOS programming operation has been developed. Excellent agreement between measurements and simulations in a large range of voltages and times is obtained, taking leakage through the gate stack and Frenkel-Poole detrapping into account. The model is exploited to predict the impact of the programming conditions on the retention behavior.

An Ultra-Thin Hybrid Floating Gate Concept for Sub-20nm NAND Flash Technologies

A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination with an Al2O3 interpoly dielectric is investigated for sub-20nm scaling. Floating gate thickness scaling down to only 5nm with excellent program/erase performance and reliability is demonstrated to address the issue of increased cell-to-cell interference. It is further shown that a hybrid floating gate also offers great benefit when used in combination with ONO, which still is the conventional interpoly dielectric layer used in state-of-the-art floating gate Flash memories.

Experimental evaluation of trapping efficiency in silicon nitride based charge trapping memories

A characterization technique capable of measuring the electrical charge injected during programming operations in silicon nitride based charge trapping memories has been developed. The trapping efficiency, defined as the fraction of carriers which gets trapped in the device with respect to the total injected charge, is extracted and is evaluated along the programming transient for a wide set of devices, featuring different material deposition techniques and different thicknesses. The trapping efficiency is found to be almost insensitive to the injection conditions, whereas it depends on the quantity of filled traps, the thickness of the trapping layer and the conduction band offset between the trapping layer and the top oxide. A higher trapping efficiency in general leads to faster programming transients and more effective programming when increasing the gate voltage.

Improvement of TANOS NAND Flash Performance by the Optimization of a Sealing Layer

We presented an optimization of an interfacial SiO2 sealing layer between the nitride and top dielectric of a TANOS stack showing a strong retention improvement thanks to an increased DeltaEc to Si3N4, that prevents vertical escape of the electrons through the top dielectric. In case of HfAlO top dielectric, it also provides a better program/disturb margin.