Dolphin Abessolo-Bidzo

CDM Simulation Based on Tester, Package and Full Integrated Circuit Modeling: Case Study

The electrostatic discharge (ESD) sensitivity of ICs with respect to the charged-device model (CDM) is strongly dependent on the IC package, the substrate resistivity, and the effectiveness of the ESD protection network. This paper presents a case study of predictive CDM circuit simulation method based on the tester, package, and full IC modeling approach.

Isolating failing sites in IC packages using time domain reflectometry: Case studies

This paper deals with Time Domain Reflectometry (TDR) technique with the aim to confirm that this tool should not be kept away from a non-destructive failure analysis process flow. An improvement of known comparative TDR methodology, the sequential comparative method, is introduced and several case studies illustrate its better efficiency to isolate complex packaging defects. Also, main limitations of the technique are studied and several hardware improvements are proposed, especially in terms of spatial resolution.

Failure localization in IC packages using time domain reflectometry: technique limitations and possible improvements

Our case study has shown the efficiency of isolating failing sites (shorts, opens) in IC packages using TDR and especially sequential comparative TDR analysis, which allowed to overcome some of TDR hardware limitations and to identify the different regions of the DUT. Currently, its possible to increase the bandwidth of the main standard TDR sources available on the market up to 70 GHz, but the main limitation is due to TDR probes which best bandwidth only reaches 20 GHz. Anyway, TDR technique has already proved to definitively take up its own place in the non-destructive failure analysis flow of FA labs beside SCAT and x-ray ones for most of common IC packages used in semiconductors industry.

Removing S-parameters on-wafer measurements parasitic elements using time domain gating: Application to transmission lines

This paper presents experimental results of removing on-wafer microwave measurements parasitic elements due to RF probes pads and interconnects using Time Domain Gating method up to 110GHz. This approach has been tested on transmission lines processed using metallization layers of NXP RF BiCMOS technology and compared with the classical OPEN/SHORT de-embedding method. The limitations and the ways to improve this technique are shown.

A study of the effect of remote CDM clamps in integrated circuits

Cross-domain signals are the largest ESD risk in integrated circuits nowadays. In this paper, a study of the effect of remote CDM clamps in ICs is presented. Predictive ESD simulations are demonstrated by TLP and vf-TLP characterizations and by means of HBM and CDM qualifications of a dedicated ESD testchip.

Circuit under pad active bipolar ESD clamp for RF applications

With the rapidly increasing RF Complexity of RF BiCMOS designs for key Mobile and Internet of Things (IoT) applications, achieving both extreme RF performance and ESD reliability requirements has become a big challenge. In this paper, a novel active bipolar clamp is proposed featuring Circuit under Pad for RF applications.

Window effects in HBM and TLP testing

We present a study of products showing systematic window effects during HBM and TLP testing. It is shown that the window effects are mainly the consequence of race conditions between different ESD current paths. Window effects are sometimes difficult to detect, but are in principle relatively easy to prevent.

Wear out effects in ESD characterization and testing

Wear out effects resulting from multiple stresses may have significant impact on ESD characterization and testing. This is shown in examples of (vf-)TLP, HMM and CDM results on test structures and products. Wear out effects lead to lower failure levels and should be minimized to obtain the correct pass/fail levels.