Theo Smedes

Harmful voltage overshoots due to turn-on behaviour of ESD protections during fast transients

Due to the reaction time of the devices, the rise time of an ESD pulse has a strong effect on the efficiency of a protection network. (vf-)TLP clearly causes different failure modes depending on the rise time. This knowledge is needed to design protections that can handle fast ESD transients.

Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels - An explantion and die protection strategy

With sownscaling of device dimensions and increased usage of automated handlers, Charged Device Model (CDM) type of Electrostatic Discharge (ESD) stress events are becoming the major readon for field returns in the Integrated Circuit (IC) industry. In the case of CDM stress, the IC is both the source of static charge and part od the discharge path. Hence CDM test results are greatly affected by the nature of the package, pin position and the location of the protection devices within the die. In this paper we present a systematic approach to understand the actual influence of these factors in the IC during a CDM event. The CDM test set-up is modeled using PSPICE circuit simulator and the discharge waveforms thus obtained are compared with the experimental observations. This model is then used to find the actual discharge current flowing through the die and the protection structures for different packages and pin positions. From this general protection strategy for CDM discharges, independent of the IC layout design is developed.

CDM Simulation Based on Tester, Package and Full Integrated Circuit Modeling: Case Study

The electrostatic discharge (ESD) sensitivity of ICs with respect to the charged-device model (CDM) is strongly dependent on the IC package, the substrate resistivity, and the effectiveness of the ESD protection network. This paper presents a case study of predictive CDM circuit simulation method based on the tester, package, and full IC modeling approach.

Designing HV active clamps for HBM robustness

Electrical measurements, physical damage analysis, and device simulation have proved that the drain junction breakdown voltage is the determining failure criterion for our HV active clamps. Using this criterion, the HBM and TLP robustness of such clamps can be accurately predicted by circuit simulation without the need for test silicon.

The application of transmission line pulse testing for the ESD analysis of integrated circuits

TLP, well known for device characterisation, applied to full integrated circuits offers valuable data for analysis of ESD behaviour. TLP is the only method to study ESD behaviour during zapping and as such provides knowledge about actual ESD current paths. As illustrated by examples, this gives valuable suggestions for improving circuit designs.

Selecting an appropriate esd protection for discrete RF power LDMOSTs

For ESD protections of RF Power MOSTs, Vt1 lowering by the RF signal, -due to the dV/dt effect-, can seriously degrade the RF performance. The use of a cascoded protection solves this problem. A new failure mechanism, related to the discharge of on-chip RF matching capacitors is presented. Adding a current limiting resistor in the protection solves this issue. Combining these solutions yields an appropriate protection for discrete RF power LDMOSTs.

ESD protection for thin gate oxides in 65 nm

Unexpected functional failures were found in the core of an IC, processed in a 65 nm technology with 1.8 nm gate oxide, after Machine Model (MM) testing, although a comprehensive rail-based protection scheme was applied. Failure analysis was performed including Obirch, backside de-processing, and SEM analysis to locate the failure in the gate oxide of several core NMOS transistors. Careful Transmission Line Pulse (TLP) measurements on NMOSTs with 1.8 nm oxides yields a mean BVox = 6.06 V and standard deviation of 0.18 V, after correction for MM test conditions. Comparison with a mean Vt1 = 5.35 V and a standard deviation of 0.15 V for ggNMOSTs shows that the tails of the BVox and Vt1 distributions overlap. This implies that connecting a gate to a drain diffusion does not guarantee adequate protection for a 1.8 nm gate oxide in a 65 nm technology.

ESD testing of devices, ICs and systems

This tutorial discusses several ways of ESD testing for devices, ICs and systems. A good understanding of the methods and the physics is required for relating test results to each other. The tutorial ends with an outlook on extensions of the current methods and a discussion on required ESD qualification levels.

PNP-eSCR ESD protection device with tunable trigger and holding voltage for high voltage applications

A novel ESD device (PNP with embedded SCR), with tunable VT1 and VH, is proposed for high voltage applications. Tuning is achieved through design and process options. The trigger mechanism is determined by the series connection of PNP(s) and diode. The holding voltage is determined by the eSCR and additional PNP(s).

The influence of technology variation on ggNMOSTs and SCRs against CDM ESD stress

In this paper we present a systematic study on the effect of process and layout variation for grounded-gate NMOSTs and LVTSCRs in a 0.18