Dominik Macko

Managing digital-system power at the system level

The increasing trend in using mobile devices causes the power consumption to become the key aspect in modern digital systems design. The current flow for low-power design involves the use of some power-reduction technique at the RTL (Register Transfer Level) or lower levels. This paper describes an extension of current low-power design flow. It proposes the power-intent specification based on UPF (Unified Power Format) in an abstract form and integrates it into a system-level model. Such an abstract level gives us the opportunity to manage power with higher efficiency.

Power-Management Specification in SystemC

Power consumption is the greatest concern in current highly-integrated hardware-system design. The power reduction is targeted mostly through power management, implementing such techniques as clock gating, power gating, or voltage and frequency scaling. Due to growing complexity, the start-point in the design has moved from the register-transfer level to the system level. However, the power management lacks the abstraction needed for the system level. Also, different power-management techniques are specified differently, complicating the specification even more. This paper targets the unified specification of power-management techniques early in the design flow. SystemC is used for describing the system functionality along with the power management. Efficiency of the proposed approach is illustrated by comparison of the unified power-management specification and the standardized approach.

Power-management high-level synthesis

Power management is an integral part of almost every new system design. It enables to keep the power under constrains, implementing such power-reduction techniques as power gating, multi-voltage design, or voltage and frequency scaling. Due to the complexity of modern designs, the system level of abstraction is adopted as a design starting point. However, the power management is not yet fully adopted at such abstraction level. In the previous research, we have proposed the abstract power-management specification, simplifying its adoption by an order of magnitude. This paper targets the power-management high-level synthesis, closing thus the gap between the system-level power management and its standard form at lower abstraction levels. Such design automation enables to reduce a number of human errors, potentially introduced by manual design. The presented experimental results validate the proposed approach.

VHDLVisualizer: HDL model visualization with simulation-based verification

The usage of the HDLs (Hardware Description Languages) in the present digital system development process is indispensable. Although, their great contribution is undeniable, they also bring about several disadvantages. The textual form of an HDL model is less illustrative for a human being than schematic representation of its structure. Moreover, simulation of such models is most commonly displayed in a waveform representation, even though sufficient for verification, it is hard-to-identify design errors. The paper presents a tool for supporting both, the model structure visualization and the simulation results in the visualized structure display.

VHDL structural model visualization

Nowadays the digital systems design is almost exclusively realized using hardware description languages (HDL). In Europe, the VHDL (Very-High-Speed Integrated Circuits HDL) is the most widely used HDL. Although HDLs brought a lot of advantages into the design process, the HDL structural models, especially on register transfer and lower layers, are harder to read than the previously used schematic representations. That is why a lot of commercial EDA (Electronic Design Automation) systems include some kind of visualization tool enabling to represent a model structure in a graphical form. However, these systems are usually too complex and expensive for the education purpose. In this case simple, easy to use visualization tool would be more appropriate. The paper deals with the problem of the structural models visualization as well as with the design and implementation of the visualization tool devoted to the VHDL structural models visualization. The presented tool offers the possibility to display the schematic view corresponding to the input VHDL model, edit the schematic layout, print it or export it to an image file. The tool preserves the model hierarchy and enables to easily switch among the respective levels. It represents an useful tool in the process of the VHDL structural model verification and debugging as well as for documentation purposes.

Verification of Power-Management Specification at Early Stages of Power-Constrained Systems Design

Nowadays, power is a dominant factor that constrains highly integrated hardware-systems designs. The implied problems of high power density, causing chip overheating, or limited power source in modern Internet-of-Things devices are most commonly dealt with the use of the dynamic power management. This method enables to use power-reduction techniques, such as clock gating, power gating, or voltage and frequency scaling. Since the adoption of power management is quite difficult in modern complex systems, there are new approaches evolving intended to simplify power-constrained systems design. We have also proposed such an approach, utilizing the system level of design abstraction and increased automation in the design process. In this paper, the proposed hybrid verification approach is described that represents an integral part of the suggested design methodology. It consists of formal and informal techniques, enabling the verification process to begin at the very early specification stage of the system development. Our approach helps a designer to create correct and consistent power-management specification and verifies whether the specified power intent is preserved after design refinement. The continuous automated verification steps can quickly find errors at early design stages and thus reduce the amount of design re-spins, which speeds-up the overall development process.

Self-managing power management unit

Power consumption is a very important aspect in almost every electronic system design. To minimize the power consumption, many advanced power-reduction techniques have been developed based on a power management. In modern systems the power management unit (PMU) is typically a complex circuit and therefore should also be targeted by power-efficient design techniques. This paper is focused on the design of self-managing PMU that can manage its own power and thus reduce the overall system power consumption. We show that the special power state machine design in the PMU allows to power inactive transition logic elements down during the idle time. We illustrate this design strategy on a simple example where approximately 70% leakage power reduction in transition logic was achieved.

Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation

Abstract Since power is the key aspect in modern systems on chips, many power-reduction techniques are adopted in the design process, mostly applied through power management. Its standard specification lacks the abstraction required by complex designs and therefore becomes difficult and error-prone. In this work, higher abstraction is introduced into the power-management specification and it is integrated with the functional model of the system. It simplifies the specification approximately 16.8 times and enables the automatic generation and verification of the equivalent standard specification. The error-prone nature of the power-management specification is thus alleviated and the difficult verification process is relieved.

Rapid power-management exploration using post-processing of the system-level simulation results

Managing the power in highly-integrated systems on chips becomes inevitable in modern designs. Complex systems require complex power management, and it is always difficult to determine whether the designed power management is the most efficient. In our previous work, we have proposed a simplified power-management specification method at the system level of abstraction. In this paper, we propose a system-level power-management evaluation approach that enables a designer to explore various power-management designs in a short time and select the best. The proposed exploration method is easy-to-use and can be used to speed-up the low-power systems development.

Rapid Estimation of Power-Management Unit Overhead from System-Level Specification

Power management becomes an integral part of hardware-systems design. In modern complex systems, the powermanagement design is not a simple task and it is quite difficult to evaluate whether the designed strategy is the best. In this paper, we propose a new method for overhead estimation of the required power-management unit, based on system-level abstract specification. It enables a designer to explore various power-management strategies in a short time and select the most suitable one. It is especially useful for ultra low-power systems, in which the power-management unit is a significant power consumer. The proposed method is simpler and faster than the existing approaches, and thus it speeds-up the low-power systems development process.