Pavel Čičák

Power-Management Specification in SystemC

Power consumption is the greatest concern in current highly-integrated hardware-system design. The power reduction is targeted mostly through power management, implementing such techniques as clock gating, power gating, or voltage and frequency scaling. Due to growing complexity, the start-point in the design has moved from the register-transfer level to the system level. However, the power management lacks the abstraction needed for the system level. Also, different power-management techniques are specified differently, complicating the specification even more. This paper targets the unified specification of power-management techniques early in the design flow. SystemC is used for describing the system functionality along with the power management. Efficiency of the proposed approach is illustrated by comparison of the unified power-management specification and the standardized approach.

Digital System Description Knowledge Assessment

The paper presents a knowledge assessment approach developed for support of Digital system description course. In the course the students should comprehend the methods and techniques used in digital system design, and gain the skills in digital systems modelling using hardware description languages (HDL). For many years the course exams used to be done only in pen and paper form. The students hated writing HDL programs on paper and the teachers disliked correcting the programs on paper as well. What is more, this type of exam has not allowed the verification of the student’s ability to debug the created model, which is the substantial part of the student’s practical skills. That is why, some years ago, we concentrated our work on designing a knowledge assessment system that will enable reliable evaluation of practical skills in the area of digital system description without substantial teacher involvement. Several applications have been developed and tested in the course. One of the best will be presented here.

Power-management high-level synthesis

Power management is an integral part of almost every new system design. It enables to keep the power under constrains, implementing such power-reduction techniques as power gating, multi-voltage design, or voltage and frequency scaling. Due to the complexity of modern designs, the system level of abstraction is adopted as a design starting point. However, the power management is not yet fully adopted at such abstraction level. In the previous research, we have proposed the abstract power-management specification, simplifying its adoption by an order of magnitude. This paper targets the power-management high-level synthesis, closing thus the gap between the system-level power management and its standard form at lower abstraction levels. Such design automation enables to reduce a number of human errors, potentially introduced by manual design. The presented experimental results validate the proposed approach.

Enhanced Classroom Presenter

Nowadays perhaps the most widespread teaching style at the university lectures is based on slides presentation using computer and data projector. Compared to the previously used “blackboard and chalk” style, data projectors brought a substantial loss of interactivity between students and teacher into the teaching process. Students are often taking notes without even thinking what they are writing down. This can in no way develop their creative thinking. Recently the “active learning” teaching style emerged and is becoming more and more preferable. To use this style in conjunction with computer and data projector the interactive presentation system is one of the basic assumptions. Among the available open-source presentation systems supporting interaction the Classroom Presenter, developed at the University of Washington, seems to be one of the most promising. The article describes the extensions that were designed and implemented to this presentation tool at the Faculty of Informatics and Information Technologies, Slovak University of Technology in Bratislava mainly to enhance the editing, import, and export possibilities of the tool.

Visualization of Verilog Digital Systems Models

Nowadays the digital systems design is almost exclusively realized using hardware description languages (HDL). Verilog belongs to the HDLs that are the most widespread especially in the United States. However, the textual HDL representation of structural model is less understandable compared the schematic one. Therefore a transformation of the structural HDL description into its graphical schematic representation is a useful function for hardware designers. In this paper the HDL Visualizator is described that was designed and implemented to support this function for Verilog structural models. The paper addresses several problems of visualization process and their possible solutions. The design and implementation of visualization tool that is able to display the schematic view as well as the simulation results of structural Verilog model is also presented.

Parallel controller design and synthesis

Petri nets provide an adequate means to visualize both sequential and parallel controller behavior. They can be used to model and visualize behavior comprising concurrency and synchronization. Strongly time dependent complex controllers can be modeled using Petri nets by introducing several extensions to the basic formalism. The contribution of the work lies in a novel type of Petri net specification, suitable for control unit design. This Petri net is a kind of Synchronous Interpreted Petri net, extended by multi-layer hierarchy and time dependencies. Moreover, a method of the Petri net transformation into synthesizable VHDL code is proposed. The capabilities of the approach are shown by means of a small example illustrating the Petri net creation and its transformation into VHDL behavioral description. The VHDL code synthesizability is demonstrated by synthesis into Spartans 3E FPGA Family and CoolRunner XPLA3 CPLDs Family.

Verification of Power-Management Specification at Early Stages of Power-Constrained Systems Design

Nowadays, power is a dominant factor that constrains highly integrated hardware-systems designs. The implied problems of high power density, causing chip overheating, or limited power source in modern Internet-of-Things devices are most commonly dealt with the use of the dynamic power management. This method enables to use power-reduction techniques, such as clock gating, power gating, or voltage and frequency scaling. Since the adoption of power management is quite difficult in modern complex systems, there are new approaches evolving intended to simplify power-constrained systems design. We have also proposed such an approach, utilizing the system level of design abstraction and increased automation in the design process. In this paper, the proposed hybrid verification approach is described that represents an integral part of the suggested design methodology. It consists of formal and informal techniques, enabling the verification process to begin at the very early specification stage of the system development. Our approach helps a designer to create correct and consistent power-management specification and verifies whether the specified power intent is preserved after design refinement. The continuous automated verification steps can quickly find errors at early design stages and thus reduce the amount of design re-spins, which speeds-up the overall development process.

Hands on Roaming Duration: Petri-Nets Modeling of a Wireless Mobile-IP Procedure in Cisco Platform

IETF RFC 2002 encountered some inefficiencies in registration process, one of the mobile-IP protocol three basic core capabilities. Mobile-IP is often far from optimal level, since all registration steps take place after the mobile node already roamed into the destined foreign subnet, causing packet losses problem while it is roaming. In this paper, a workaround is developed, mapping the roaming behavior to mobile-IP registration process, to model a CIA: communication inter-agents procedure. The procedure supposes an early registration of the mobile node, to a subnet predicted to roam into, using a triple-R home agent-based registration. This enabled to reduce roaming duration, eliminate packet losses, and bridge the gap between subnets, an area that until now has been largely neglected. Analytical performance results of state-transition Petri-nets model, as a function of different network parameters, are presented. Configuration file during implementation setup on Cisco platform Router-1760 using IOS 12.3 (15)T is created. Simulation results from Simulink Matlab are illustrated, to verify the effectiveness of CIA with much lower packet delays. Packets flow is reported between subnets for no more gaps of losses

Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation

Abstract Since power is the key aspect in modern systems on chips, many power-reduction techniques are adopted in the design process, mostly applied through power management. Its standard specification lacks the abstraction required by complex designs and therefore becomes difficult and error-prone. In this work, higher abstraction is introduced into the power-management specification and it is integrated with the functional model of the system. It simplifies the specification approximately 16.8 times and enables the automatic generation and verification of the equivalent standard specification. The error-prone nature of the power-management specification is thus alleviated and the difficult verification process is relieved.

Search using a swarm of unmanned aerial vehicles

Unmanned aerial vehicles are becoming an effective platform to perform all kinds of civil missions nowadays. This paper focuses on path planning for multiple unmanned aerial vehicles devices performing search missions. This planning consists of several logical steps — first, an area must be split into smaller logical areas, then the search algorithm is selected, ground path is generated and transformed into aerial path. All these steps are described and the most common approaches are detailed. We also mention approaches to create network using drones to further optimize search procedure.