Dominik Stoffel

Record and play: a structural fixed point iteration for sequential circuit verification

This paper proposes a technique for sequential logic equivalence checking by a structural fixed point iteration. Verification is performed by expanding the circuit into an iterative circuit array and by proving equivalence of each time frame by well-known combinational verification techniques. These exploit structural similarity between designs by local circuit transformations. Starting from the initial state, for each time frame the performed circuit transformations are stored (recorded) in an instruction queue. In subsequent time frames the instruction queue is re-used (played) and updated when necessary. At some point the instruction queue does not need to be modified any more and is valid in all subsequent time frames. Thus, a fixed point is reached and machine equivalence is proved by induction. Experimental results show the great promise of this approach to verify circuits after resynthesis and retiming.

Verification of integer multipliers on the arithmetic bit level

One of the most severe shortcomings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. We propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. Experimental results show the promise of our approach.

AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks

This paper presents a technique to determine prime implicants in multi-level combinational networks. The method is based on a graph representation of Boolean functions called AND/OR reasoning graphs. This representation follows from a search strategy to solve the satisfiability problem that is radically different from conventional search for this purpose (such as exhaustive simulation, backtracking, BDDs). The paper shows how to build AND/OR reasoning graphs for arbitrary combinational circuits and proves basic theoretical properties of the graphs. It will be demonstrated that AND/OR reasoning graphs allow us to naturally extend basic notions of two-level switching circuit theory to multi-level circuits. In particular, the notions of prime implicants and permissible prime implicants are defined for multi-level circuits and it is proved that AND/OR reasoning graphs represent all these implicants. Experimental results are shown for PLA factorization.

Accelerating Boolean Implications with FPGAs

We present the FPGA implementation of an algorithm [4] that computes implications between signal values in a boolean network. The research was performed as a master’s thesis [5] at the University of Frankfurt. The recursive algorithm is rather complex for a hardware realization and therefore the FPGA implementation is an interesting example for the potential of reconfigurable computing beyond systolic algorithms.

AND/OR Reasoning Graphs

This chapter develops a general view of the recursive learning procedure of Chapter 3 and presents a generalization of the technique. The main focus is on the basic search process underlying recursive learning. It is shown that the search process in recursive learning is a special instance of an AND/OR search. This leads to a basic reasoning scheme in Boolean networks based on AND/OR reasoning graphs. AND/OR reasoning graphs can identify implications and implicants in multi-level circuits so that basic concepts of two-level circuit theory can be extended and applied to multi-level circuits. This chapter elaborates properties of AND/OR reasoning graphs that are useful in solving design automation problems. Applications will be described in Chapters 5 and 6.