Joakim Urdahl

Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs

A formal methodology for system verification of system-on-chip (SoC) designs is proposed. It ensures that system-level models are created that are sound abstractions of the concrete implementations at the register transfer level (RTL). For each SoC module at the RTL, an abstract description is obtained by path predicate abstraction. Path predicate abstraction is introduced based on the notion of operational graph coloring. It is shown to what extent the proposed abstraction mechanism is related to the notion of a stuttering bisimulation employed in the field of theorem proving. The proposed methodology, however, does not rely on theorem proving but is entirely based on standard techniques of property checking. Path predicate abstraction leads to time-abstract system models that can be composed into abstract system models. We demonstrate the practical feasibility of our approach by two comprehensive industrial case studies.

Properties first? a new design methodology for hardware, and its perspectives in safety analysis

This paper discusses the possible role of formal verification techniques in system-level design flows. It is argued that the role of formal verification techniques should not be limited to “bug hunting” alone. Instead, formal technology should be applied in such a way that a formal relationship is provided between an abstract system model and its concrete implementation at the Register Transfer Level (RTL). In order to avoid the high efforts associated with verification by property checking this paper advocates for a top-down methodology where abstract properties are automatically generated from a system-level description and are later refined along the design process. One advantage of this methodology is to obtain a formally verified design at lower costs when compared to conventional property checking. Moreover, the proposed approach can be beneficial also when analyzing non-functional design targets. The paper demonstrates this for safety. We present experimental results that show how the effects of Single Event Upsets (SEUs) at the gate level of an SoC module can be related to safety requirements at the systems transaction level with formal precision.

System verification of concurrent RTL modules by compositional path predicate abstraction

A new methodology for formal system verification of System-on-Chip (SoC) designs is proposed. It does not only ensure correctness of the system-level models but also of the concrete implementation at the Register-Transfer-Level (RTL). For each SoC module at the RTL an abstract description is obtained by path predicate abstraction. Since this leads to time-abstract system models the main challenge is to deal with the concurrency between the individual RTL components. We propose a compositional scheme describing the communication between SoC modules independently of their individual processing speed. The composed abstract system is modeled as an asynchronous composition and can be verified using the SPIN model checker. We demonstrate the practical feasibility of our approach by a comprehensive case study based on Infineons FPI Bus.

Dynamic Power Optimization Based on Formal Property Checking of Operations

Formal verification techniques for System-on-Chips (SoCs) have matured significantly over the last years. They can penetrate deeply into a design to exhibit complex functional dependencies between various design components in terms of detailed logic and temporal relationships. The purpose of this paper is to show how this knowledge can be leveraged to optimize the dynamic power consumptions of SoC modules. Starting from a set of SVA properties fulfilling the criterion of full functional coverage, this paper proposes a new approach to clock gating based on an operational design view as introduced by existing property checking methodologies. The paper shows how certain flip-flops can be identified that are irrelevant during certain times of specific operations and therefore can be clockgated. In an industrial case study savings in power consumption of 20 % were achieved demonstrating the great potential of the proposed approach.

Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design

This paper surveys the state-of-the-art in operation-based property checking and describes how this technique can be used to conceptualize on a design at the Register-Transfer-Level (RTL). The paper argues that this technique can contribute to closing the semantic gap between system level design descriptions and the RTL and, thus, opens new possibilities for solving the power closure problem. The semantics of the high-level model are defined in terms of properties to be proven on the concrete RTL. The paper surveys a methodology to create sound abstractions and elaborates their possible role in a power-aware design flow. Specifically, it is demonstrated that the availability of a formal specification at an abstract level can be exploited for energy estimations at the system level as well as for deriving power optimizations at the RTL. First experimental results will be shown that demonstrate this optimization potential and confirm the correlation between energy consumption and operations which are the basic building blocks of the proposed abstract models.